re PR target/67126 ([SH] gcc.target/sh/pr51244-12.c failures)
gcc/ PR target/67126 * config/sh/sh.md (*reg_lsb_t): Emit bld insn on SH2A. (*mov_t_msb_neg): Rewrite negc pattern. gcc/testsuite/ PR target/67126 * gcc.target/sh/pr51244-12.c: Adjust testcase. * gcc.target/sh/pr54236-2.c: Likewise. From-SVN: r227957
This commit is contained in:
Oleg Endo
parent
625c33c4e8
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0a775f1a4b
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@ -1,3 +1,9 @@
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2015-09-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/67126
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* config/sh/sh.md (*reg_lsb_t): Emit bld insn on SH2A.
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(*mov_t_msb_neg): Rewrite negc pattern.
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2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Cleanup
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@ -4204,7 +4204,7 @@ label:
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;; Let combine see that we can get the MSB and LSB into the T bit
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;; via shll and shlr. This allows it to plug it into insns that can have
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;; the T bit as an input (e.g. addc).
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;; FIXME: On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
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;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
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(define_insn_and_split "*reg_lsb_t"
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[(set (reg:SI T_REG)
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(and:SI (match_operand:SI 0 "arith_reg_operand")
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@ -4214,7 +4214,8 @@ label:
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"&& 1"
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[(const_int 0)]
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{
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emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[0]));
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emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
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: gen_shlr (gen_reg_rtx (SImode), operands[0]));
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})
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(define_insn_and_split "*reg_msb_t"
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@ -11979,41 +11980,31 @@ label:
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[(set (match_dup 0) (reg:SI T_REG))
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(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
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;; Use negc to store the T bit in a MSB of a reg in the following way:
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;; T = 0: 0x80000000 -> reg
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;; T = 1: 0x7FFFFFFF -> reg
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;; This works because 0 - 0x80000000 = 0x80000000.
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(define_insn_and_split "*mov_t_msb_neg"
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[(set (match_operand:SI 0 "arith_reg_dest")
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(minus:SI (const_int -2147483648) ;; 0x80000000
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(match_operand 1 "treg_set_expr")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1 && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (negt_reg_operand (operands[1], VOIDmode))
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{
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emit_insn (gen_addc (operands[0],
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force_reg (SImode, const0_rtx),
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force_reg (SImode, GEN_INT (2147483647))));
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DONE;
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}
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sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
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if (ti.remove_trailing_nott ())
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emit_insn (gen_addc (operands[0],
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force_reg (SImode, const0_rtx),
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force_reg (SImode, GEN_INT (2147483647))));
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else
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emit_insn (gen_negc (operands[0],
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force_reg (SImode, GEN_INT (-2147483648LL))));
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DONE;
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})
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;; 0x7fffffff + T
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;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
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;;
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;; Notice that 0 - 0x80000000 = 0x80000000.
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;; Single bit tests are usually done with zero_extract. On non-SH2A this
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;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
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;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
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;; This is a special case of the generic treg_set_expr pattern and thus has
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;; to come first or it will never match.
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(define_insn_and_split "*mov_t_msb_neg"
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[(set (match_operand:SI 0 "arith_reg_dest")
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(plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
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(const_int 1))
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(const_int 2147483647)))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& can_create_pseudo_p ()"
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[(parallel [(set (match_dup 0)
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(plus:SI (zero_extract:SI (match_dup 1)
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(const_int 1) (const_int 0))
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(const_int 2147483647)))
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(clobber (reg:SI T_REG))])])
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(define_insn_and_split "*mov_t_msb_neg"
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[(set (match_operand:SI 0 "arith_reg_dest")
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(plus:SI (match_operand 1 "treg_set_expr")
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@ -1,3 +1,9 @@
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2015-09-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/67126
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* gcc.target/sh/pr51244-12.c: Adjust testcase.
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* gcc.target/sh/pr54236-2.c: Likewise.
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2015-09-20 Oleg Endo <olegendo@gcc.gnu.org>
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* gcc.target/sh/pr43417.c: Move target independent test to ...
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@ -4,8 +4,14 @@
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/* { dg-do compile } */
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/* { dg-options "-O1" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
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/* { dg-final { scan-assembler-times "negc" 15 } } */
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/* { dg-final { scan-assembler-times "addc" 3 } } */
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/* { dg-final { scan-assembler-times "negc" 15 { target { ! sh2a } } } } */
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/* { dg-final { scan-assembler-times "addc" 3 { target { ! sh2a } } } } */
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/* { dg-final { scan-assembler-times "negc" 13 { target { sh2a } } } } */
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/* { dg-final { scan-assembler-times "addc" 5 { target { sh2a } } } } */
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/* { dg-final { scan-assembler-times "bld" 2 { target { sh2a } } } } */
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/* { dg-final { scan-assembler-not "movrt|#-1|add\t|sub\t|movt" } } */
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int
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@ -5,7 +5,6 @@
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/* { dg-options "-O1" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
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/* { dg-final { scan-assembler-times "addc" 36 } } */
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/* { dg-final { scan-assembler-times "shlr" 22 } } */
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/* { dg-final { scan-assembler-times "shll" 14 } } */
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/* { dg-final { scan-assembler-times "add\tr" 12 } } */
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/* { dg-final { scan-assembler-not "movt" } } */
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@ -17,115 +16,118 @@
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/* { dg-final { scan-assembler-times "bclr\t#0" 1 { target { sh2a } } } } */
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/* { dg-final { scan-assembler-times "shlr" 22 { target { ! sh2a } } } } */
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/* { dg-final { scan-assembler-not "shlr" { target { sh2a } } } } */
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int
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test_000 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + (b & 1);
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}
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int
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test_001 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + b + (c & 1);
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}
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int
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test_002 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + b + c + (d & 1);
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}
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int
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test_003 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return (b & 1) + a;
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}
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int
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test_004 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + (c & 1) + b;
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}
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int
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test_005 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + b + (d & 1) + c;
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}
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int
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test_006 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return (c & 1) + a + b;
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}
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int
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test_007 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + (d & 1) + b + c;
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}
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int
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test_008 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return (d & 1) + a + b + c;
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}
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int
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test_009 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + b + (b & 1);
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}
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int
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test_010 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + (b & 1) + b;
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}
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int
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test_011 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return (b & 1) + a + b;
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}
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int
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test_012 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + b + d + (b & 1);
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}
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int
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test_013 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + d + (b & 1) + b;
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}
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int
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test_014 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return a + (b & 1) + d + b;
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}
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int
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test_015 (int a, int c, int b, int d)
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{
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// 1x shlr, 1x add, 1x addc
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// 1x shlr/bld, 1x add, 1x addc
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return (b & 1) + a + d + b;
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}
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@ -140,42 +142,42 @@ test_016 (int a, int b, int c, int d)
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int
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test_017 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + a + (a & 1);
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}
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int
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test_018 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return a + (a & 1) + a;
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}
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int
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test_019 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return (a & 1) + a + a;
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}
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int
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test_020 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return b + b + (a & 1);
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}
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int
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test_021 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return b + (a & 1) + b;
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}
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int
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test_022 (int a, int b, int c, int d)
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{
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// 1x shlr, 1x addc
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// 1x shlr/bld, 1x addc
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return (a & 1) + b + b;
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}
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