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[AArch64]Add vec_shr pattern for 64-bit vectors using ush{l,r}; enable tests.

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gcc/:
 
	* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.

gcc/testsuite/:

	* lib/target-supports.exp (check_effective_target_whole_vector_shift):
	Add aarch64{,_be}.

From-SVN: r218022
This commit is contained in:
Alan Lawrence 2014-11-24 15:23:28 +00:00 committed by Alan Lawrence
parent d9e80f4944
commit 0b4eefd5a8
4 changed files with 25 additions and 0 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2014-11-24 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.
2014-11-24 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):

15
gcc/config/aarch64/aarch64-simd.md
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@ -795,6 +795,21 @@
}
)
;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero.
(define_insn "vec_shr_<mode>"
[(set (match_operand:VD 0 "register_operand" "=w")
(lshiftrt:VD (match_operand:VD 1 "register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")))]
"TARGET_SIMD"
{
if (BYTES_BIG_ENDIAN)
return "ushl %d0, %d1, %2";
else
return "ushr %d0, %d1, %2";
}
[(set_attr "type" "neon_shift_imm")]
)
(define_insn "aarch64_simd_vec_setv2di"
[(set (match_operand:V2DI 0 "register_operand" "=w,w")
(vec_merge:V2DI

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2014-11-24 Alan Lawrence <alan.lawrence@arm.com>
* lib/target-supports.exp (check_effective_target_whole_vector_shift):
Add aarch64{,_be}.
2014-11-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/63679

1
gcc/testsuite/lib/target-supports.exp
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@ -3399,6 +3399,7 @@ proc check_effective_target_vect_shift { } {
proc check_effective_target_whole_vector_shift { } {
if { [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [istarget ia64-*-*]
|| [istarget aarch64*-*-*]
|| ([check_effective_target_arm32]
&& [check_effective_target_arm_little_endian])
|| ([istarget mips*-*-*]