re PR debug/43177 (Handle at least simple cases of reversible insns in debug info)
PR debug/43177 * var-tracking.c (loc_cmp): Don't assert VALUEs have the same mode. (VAL_EXPR_HAS_REVERSE): Define. (reverse_op): New function. (add_stores): For reversible operations add an extra MO_VAL_USE. * gcc.dg/guality/pr43177.c: New test. From-SVN: r157188
This commit is contained in:
Jakub Jelinek
parent
7428bc268d
commit
0c5863c253
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@ -0,0 +1,36 @@
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/* { dg-do run } */
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/* { dg-options "-g" } */
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void __attribute__((noinline))
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bar (long x)
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{
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asm volatile ("" : : "r" (x) : "memory");
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}
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long __attribute__((noinline))
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foo (long x)
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{
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long l = x + 3;
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bar (l);/* { dg-final { gdb-test 15 "l" "10" } } */
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bar (l);/* { dg-final { gdb-test 15 "x" "7" } } */
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return l;
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}
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long __attribute__((noinline))
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baz (int x)
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{
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long l = x + 3;
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bar (l);/* { dg-final { gdb-test 24 "l" "10" } } */
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bar (l);/* { dg-final { gdb-test 24 "x" "7" } } */
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return l;
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}
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int
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main (void)
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{
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int i;
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asm volatile ("" : "=r" (i) : "0" (7));
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foo (i);
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baz (i);
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return 0;
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}
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@ -2478,7 +2478,10 @@ loc_cmp (rtx x, rtx y)
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{
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if (GET_CODE (y) != VALUE)
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return -1;
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gcc_assert (GET_MODE (x) == GET_MODE (y));
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/* Don't assert the modes are the same, that is true only
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when not recursing. (subreg:QI (value:SI 1:1) 0)
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and (subreg:QI (value:DI 2:2) 0) can be compared,
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even when the modes are different. */
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if (canon_value_cmp (x, y))
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return -1;
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else
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@ -4678,6 +4681,10 @@ count_with_sets (rtx insn, struct cselib_set *sets, int n_sets)
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MO_CLOBBER as well. */
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#define VAL_EXPR_IS_CLOBBERED(x) \
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(RTL_FLAG_CHECK1 ("VAL_EXPR_IS_CLOBBERED", (x), CONCAT)->unchanging)
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/* Whether the location is a CONCAT of the MO_VAL_SET expression and
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a reverse operation that should be handled afterwards. */
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#define VAL_EXPR_HAS_REVERSE(x) \
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(RTL_FLAG_CHECK1 ("VAL_EXPR_HAS_REVERSE", (x), CONCAT)->return_val)
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/* Add uses (register and memory references) LOC which will be tracked
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to VTI (bb)->mos. INSN is instruction which the LOC is part of. */
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@ -4863,6 +4870,92 @@ add_uses_1 (rtx *x, void *cui)
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for_each_rtx (x, add_uses, cui);
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}
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/* Attempt to reverse the EXPR operation in the debug info. Say for
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reg1 = reg2 + 6 even when reg2 is no longer live we
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can express its value as VAL - 6. */
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static rtx
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reverse_op (rtx val, const_rtx expr)
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{
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rtx src, arg, ret;
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cselib_val *v;
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enum rtx_code code;
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if (GET_CODE (expr) != SET)
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return NULL_RTX;
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if (!REG_P (SET_DEST (expr)) || GET_MODE (val) != GET_MODE (SET_DEST (expr)))
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return NULL_RTX;
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src = SET_SRC (expr);
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switch (GET_CODE (src))
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{
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case PLUS:
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case MINUS:
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case XOR:
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case NOT:
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case NEG:
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case SIGN_EXTEND:
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case ZERO_EXTEND:
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break;
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default:
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return NULL_RTX;
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}
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if (!REG_P (XEXP (src, 0)) || !SCALAR_INT_MODE_P (GET_MODE (src)))
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return NULL_RTX;
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v = cselib_lookup (XEXP (src, 0), GET_MODE (XEXP (src, 0)), 0);
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if (!v || !cselib_preserved_value_p (v))
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return NULL_RTX;
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switch (GET_CODE (src))
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{
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case NOT:
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case NEG:
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if (GET_MODE (v->val_rtx) != GET_MODE (val))
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return NULL_RTX;
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ret = gen_rtx_fmt_e (GET_CODE (src), GET_MODE (val), val);
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break;
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case SIGN_EXTEND:
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case ZERO_EXTEND:
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ret = gen_lowpart_SUBREG (GET_MODE (v->val_rtx), val);
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break;
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case XOR:
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code = XOR;
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goto binary;
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case PLUS:
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code = MINUS;
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goto binary;
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case MINUS:
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code = PLUS;
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goto binary;
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binary:
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if (GET_MODE (v->val_rtx) != GET_MODE (val))
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return NULL_RTX;
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arg = XEXP (src, 1);
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if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
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{
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arg = cselib_expand_value_rtx (arg, scratch_regs, 5);
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if (arg == NULL_RTX)
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return NULL_RTX;
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if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
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return NULL_RTX;
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}
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ret = simplify_gen_binary (code, GET_MODE (val), val, arg);
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if (ret == val)
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/* Ensure ret isn't VALUE itself (which can happen e.g. for
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(plus (reg1) (reg2)) when reg2 is known to be 0), as that
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breaks a lot of routines during var-tracking. */
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ret = gen_rtx_fmt_ee (PLUS, GET_MODE (val), val, const0_rtx);
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break;
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default:
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gcc_unreachable ();
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}
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return gen_rtx_CONCAT (GET_MODE (v->val_rtx), v->val_rtx, ret);
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}
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/* Add stores (register and memory references) LOC which will be tracked
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to VTI (bb)->mos. EXPR is the RTL expression containing the store.
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CUIP->insn is instruction which the LOC is part of. */
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@ -4879,6 +4972,7 @@ add_stores (rtx loc, const_rtx expr, void *cuip)
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bool track_p = false;
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cselib_val *v;
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bool resolve, preserve;
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rtx reverse;
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if (type == MO_CLOBBER)
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return;
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@ -5082,6 +5176,16 @@ add_stores (rtx loc, const_rtx expr, void *cuip)
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*/
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if (GET_CODE (PATTERN (cui->insn)) != COND_EXEC)
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{
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reverse = reverse_op (v->val_rtx, expr);
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if (reverse)
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{
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loc = gen_rtx_CONCAT (GET_MODE (mo->u.loc), loc, reverse);
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VAL_EXPR_HAS_REVERSE (loc) = 1;
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}
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}
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mo->u.loc = loc;
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if (track_p)
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@ -5367,10 +5471,17 @@ compute_bb_dataflow (basic_block bb)
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case MO_VAL_SET:
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{
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rtx loc = VTI (bb)->mos[i].u.loc;
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rtx val, vloc, uloc;
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rtx val, vloc, uloc, reverse = NULL_RTX;
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vloc = uloc = XEXP (loc, 1);
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val = XEXP (loc, 0);
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vloc = loc;
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if (VAL_EXPR_HAS_REVERSE (loc))
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{
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reverse = XEXP (loc, 1);
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vloc = XEXP (loc, 0);
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}
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uloc = XEXP (vloc, 1);
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val = XEXP (vloc, 0);
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vloc = uloc;
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if (GET_CODE (val) == CONCAT)
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{
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@ -5443,6 +5554,10 @@ compute_bb_dataflow (basic_block bb)
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var_regno_delete (out, REGNO (uloc));
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val_store (out, val, vloc, insn, true);
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if (reverse)
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val_store (out, XEXP (reverse, 0), XEXP (reverse, 1),
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insn, false);
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}
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break;
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@ -7012,10 +7127,17 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
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case MO_VAL_SET:
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{
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rtx loc = VTI (bb)->mos[i].u.loc;
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rtx val, vloc, uloc;
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rtx val, vloc, uloc, reverse = NULL_RTX;
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vloc = uloc = XEXP (loc, 1);
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val = XEXP (loc, 0);
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vloc = loc;
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if (VAL_EXPR_HAS_REVERSE (loc))
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{
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reverse = XEXP (loc, 1);
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vloc = XEXP (loc, 0);
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}
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uloc = XEXP (vloc, 1);
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val = XEXP (vloc, 0);
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vloc = uloc;
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if (GET_CODE (val) == CONCAT)
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{
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@ -7083,6 +7205,10 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
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val_store (set, val, vloc, insn, true);
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if (reverse)
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val_store (set, XEXP (reverse, 0), XEXP (reverse, 1),
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insn, false);
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emit_notes_for_changes (NEXT_INSN (insn), EMIT_NOTE_BEFORE_INSN,
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set->vars);
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}
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