re PR target/54236 ([SH] Improve addc and subc insn utilization)
PR target/54236 * config/sh/sh.md (addc): Add commutative modifier. (*addc, *minus_plus_one, *subc, *negc): New insns and splits. PR target/54236 * gcc.target/sh/pr54236-1.c: New. From-SVN: r190459
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Oleg Endo
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@ -1,3 +1,9 @@
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2012-08-16 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/54236
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* config/sh/sh.md (addc): Add commutative modifier.
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(*addc, *minus_plus_one, *subc, *negc): New insns and splits.
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2012-08-16 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/39423
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@ -1686,7 +1686,7 @@
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(define_insn "addc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
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(match_operand:SI 2 "arith_reg_operand" "r"))
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(reg:SI T_REG)))
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(set (reg:SI T_REG)
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@ -1695,6 +1695,76 @@
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"addc %2,%0"
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[(set_attr "type" "arith")])
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;; A simplified version of the addc insn, where the exact value of the
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;; T bit doesn't matter. This is easier for combine to pick up.
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;; We allow a reg or 0 for one of the operands in order to be able to
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;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
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;; as needed.
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(define_insn "*addc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
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(match_operand:SI 2 "arith_reg_or_0_operand" "r"))
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(match_operand:SI 3 "t_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"addc %2,%0"
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[(set_attr "type" "arith")])
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;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
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;; better, if the sett insn can be done early.
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(define_insn_and_split "*addc"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
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(match_operand:SI 2 "arith_reg_operand" ""))
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(const_int 1)))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(set (reg:SI T_REG) (const_int 1))
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(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
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(reg:SI T_REG)))
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(clobber (reg:SI T_REG))])])
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;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
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;; matched. Split this up into a simple sub add sequence, as this will save
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;; us one sett insn.
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(define_insn_and_split "*minus_plus_one"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
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(match_operand:SI 2 "arith_reg_operand" ""))
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(const_int 1)))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
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;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
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;; If the 0 constant can be CSE-ed, this becomes a one instruction
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;; operation, as opposed to sequences such as
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;; movt r2
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;; add r2,r3
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;;
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;; Even if the constant is not CSE-ed, a sequence such as
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;; mov #0,r2
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;; addc r2,r3
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;; can be scheduled much better since the load of the constant can be
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;; done earlier, before any comparison insns that store the result in
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;; the T bit.
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(define_insn_and_split "*addc"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(plus:SI (match_operand:SI 1 "t_reg_operand" "")
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(match_operand:SI 2 "arith_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(plus:SI (plus:SI (match_dup 2) (const_int 0))
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(match_dup 1)))
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(clobber (reg:SI T_REG))])])
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "arith_reg_operand" "")
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(plus:SI (match_operand:SI 1 "arith_operand" "")
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@ -1805,6 +1875,63 @@
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"subc %2,%0"
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[(set_attr "type" "arith")])
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;; A simplified version of the subc insn, where the exact value of the
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;; T bit doesn't matter. This is easier for combine to pick up.
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;; We allow a reg or 0 for one of the operands in order to be able to
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;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
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;; as needed.
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(define_insn "*subc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
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(match_operand:SI 2 "arith_reg_or_0_operand" "r"))
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(match_operand:SI 3 "t_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"subc %2,%0"
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[(set_attr "type" "arith")])
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;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
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;; better, if the sett insn can be done early.
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;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
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(define_insn_and_split "*subc"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
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(match_operand:SI 2 "arith_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(set (reg:SI T_REG) (const_int 1))
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(parallel [(set (match_dup 0)
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(minus:SI (minus:SI (match_dup 2) (match_dup 1))
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(reg:SI T_REG)))
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(clobber (reg:SI T_REG))])])
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;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
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;; If the 0 constant can be CSE-ed, this becomes a one instruction
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;; operation, as opposed to sequences such as
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;; movt r2
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;; sub r2,r3
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;;
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;; Even if the constant is not CSE-ed, a sequence such as
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;; mov #0,r2
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;; subc r2,r3
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;; can be scheduled much better since the load of the constant can be
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;; done earlier, before any comparison insns that store the result in
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;; the T bit.
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(define_insn_and_split "*subc"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(minus:SI (match_operand:SI 1 "arith_reg_operand" "")
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(match_operand:SI 2 "t_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(minus:SI (minus:SI (match_dup 1) (const_int 0))
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(match_dup 2)))
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(clobber (reg:SI T_REG))])])
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(define_insn "*subsi3_internal"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
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@ -4530,6 +4657,19 @@ label:
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"negc %1,%0"
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[(set_attr "type" "arith")])
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;; A simplified version of the negc insn, where the exact value of the
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;; T bit doesn't matter. This is easier for combine to pick up.
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;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
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;; extra patterns for this case.
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(define_insn "*negc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
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(match_operand:SI 2 "t_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"negc %1,%0"
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[(set_attr "type" "arith")])
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(define_insn "*negdi_media"
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[(set (match_operand:DI 0 "arith_reg_dest" "=r")
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(neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
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@ -1,4 +1,9 @@
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2012-08-17 Hans-Peter Nilsson <hp@axis.com>
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2012-08-16 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/54236
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* gcc.target/sh/pr54236-1.c: New.
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2012-08-16 Hans-Peter Nilsson <hp@axis.com>
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* lib/target-supports.exp (check_effective_target_sync_int_long)
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(check_effective_target_sync_char_short): Enable for crisv32-*
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76
gcc/testsuite/gcc.target/sh/pr54236-1.c
Normal file
76
gcc/testsuite/gcc.target/sh/pr54236-1.c
Normal file
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/* Tests to check the utilization of addc, subc and negc instructions in
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special cases. If everything works as expected we won't see any
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movt instructions in these cases. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O1" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
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/* { dg-final { scan-assembler-times "addc" 3 } } */
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/* { dg-final { scan-assembler-times "subc" 3 } } */
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/* { dg-final { scan-assembler-times "sett" 4 } } */
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/* { dg-final { scan-assembler-times "negc" 1 } } */
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/* { dg-final { scan-assembler-not "movt" } } */
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int
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test_00 (int a, int b, int c, int d)
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{
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/* 1x addc, 1x sett */
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return a + b + 1;
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}
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int
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test_01 (int a, int b, int c, int d)
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{
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/* 1x addc */
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return a + (c == d);
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}
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int
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test_02 (int a, int b, int c, int d)
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{
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/* 1x subc, 1x sett */
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return a - b - 1;
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}
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int
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test_03 (int a, int b, int c, int d)
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{
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/* 1x subc */
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return a - (c == d);
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}
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int
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test_04 (int a, int b, int c, int d)
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{
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/* 1x addc, 1x sett */
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return a + b + c + 1;
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}
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int
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test_05 (int a, int b, int c, int d)
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{
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/* 1x subc, 1x sett */
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return a - b - c - 1;
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}
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int
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test_06 (int a, int b, int c, int d)
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{
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/* 1x negc */
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return 0 - a - (b == c);
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}
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int
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test_07 (int *vec)
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{
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/* Must not see a 'sett' or 'addc' here.
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This is a case where combine tries to produce
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'a + (0 - b) + 1' out of 'a - b + 1'. */
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int z = vec[0];
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int vi = vec[1];
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int zi = vec[2];
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if (zi != 0 && z < -1)
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vi -= (((vi >> 7) & 0x01) << 1) - 1;
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return vi;
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}
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