backport: [multiple changes]
2012-09-06 Uros Bizjak <ubizjak@gmail.com> * config/i386/sse.md (<sse4_1_avx2>_pblendvb): Use reg_not_xmm0_operand_maybe_avx as operand 0 constraint. 2012-09-06 Uros Bizjak <ubizjak@gmail.com> Backport from mainline 2012-08-11 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (isa): Add fma and fma4. (enabled): Handle fma and fma4. * config/i386/sse.md (*fma_fmadd_<mode>): Merge *fma4_fmadd_<mode>. (*fma_fmsub_<mode>): Merge *fma4_fmsub_<mode>. (*fma_fnmadd_<mode>): Merge *fma4_fnmadd_<mode>. (*fma_fnmsub_<mode>): Merge *fma4_fnmsub_<mode>. (*fma_fmaddsub_<mode>): Merge *fma4_fmaddsub_<mode>. (*fma_fmsubadd_<mode>): Merge *fma4_fmsubadd_<mode>. 2012-08-10 Uros Bizjak <ubizjak@gmail.com> * config/i386/sse.md (*fma_fmadd_<mode>, *fma_fmsub_<mode>, *fma_fnmadd_<mode>, *fma_fnmsub_<mode>, *fma_fmaddsub_<mode>, *fma_fmsubadd_<mode>): Move FMA3 insn patterns before FMA4 patterns. From-SVN: r191032
This commit is contained in:
Uros Bizjak
parent
c2173bb41b
commit
0c7a296cc3
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@ -1,3 +1,28 @@
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2012-09-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (<sse4_1_avx2>_pblendvb): Use
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reg_not_xmm0_operand_maybe_avx as operand 0 constraint.
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2012-09-06 Uros Bizjak <ubizjak@gmail.com>
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Backport from mainline
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2012-08-11 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (isa): Add fma and fma4.
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(enabled): Handle fma and fma4.
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* config/i386/sse.md (*fma_fmadd_<mode>): Merge *fma4_fmadd_<mode>.
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(*fma_fmsub_<mode>): Merge *fma4_fmsub_<mode>.
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(*fma_fnmadd_<mode>): Merge *fma4_fnmadd_<mode>.
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(*fma_fnmsub_<mode>): Merge *fma4_fnmsub_<mode>.
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(*fma_fmaddsub_<mode>): Merge *fma4_fmaddsub_<mode>.
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(*fma_fmsubadd_<mode>): Merge *fma4_fmsubadd_<mode>.
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2012-08-10 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (*fma_fmadd_<mode>, *fma_fmsub_<mode>,
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*fma_fnmadd_<mode>, *fma_fnmsub_<mode>, *fma_fmaddsub_<mode>,
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*fma_fmsubadd_<mode>): Move FMA3 insn patterns before FMA4 patterns.
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2012-09-06 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/54498
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@ -23,7 +48,7 @@
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2012-09-05 Georg-Johann Lay <avr@gjlay.de>
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Backport from 2012-09-05 mainline r190697.
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PR target/54461
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* config.gcc (tm_file,target=avr-*-*): Add avr/avrlibc.h if
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configured --with-avrlibc.
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@ -39,8 +64,8 @@
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Backport from 2012-09-04 mainline r190919
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PR target/45070
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* config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value of size
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less than 4 bytes by using macro ARM_NUM_INTS.
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* config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value
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of size less than 4 bytes by using macro ARM_NUM_INTS.
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(thumb1_unexpanded_epilogue): Use macro ARM_NUM_INTS.
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2012-09-04 Richard Henderson <rth@redhat.com>
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@ -52,8 +77,7 @@
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Backport from 2012-09-04 mainline r190920
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PR target/54476
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* config/avr/avr.c (avr_expand_delay_cycles): Mask operand with
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SImode.
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* config/avr/avr.c (avr_expand_delay_cycles): Mask operand with SImode.
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2012-09-04 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
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@ -628,7 +628,8 @@
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(define_attr "movu" "0,1" (const_string "0"))
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;; Used to control the "enabled" attribute on a per-instruction basis.
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(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2"
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(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,
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bmi2,fma,fma4"
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(const_string "base"))
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(define_attr "enabled" ""
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@ -642,6 +643,9 @@
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(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
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(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
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(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
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(eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
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(eq_attr "isa" "fma4")
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(symbol_ref "TARGET_FMA4 && !TARGET_FMA")
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]
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(const_int 1)))
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@ -395,8 +395,6 @@
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;; Mix-n-match
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(define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
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(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
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;; Mapping of immediate bits for blend instructions
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(define_mode_attr blendbits
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[(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
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@ -1687,28 +1685,12 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; FMA4 floating point multiply/accumulate instructions. This
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;; includes the scalar version of the instructions as well as the
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;; vector.
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;; FMA floating point multiply/accumulate instructions. These include
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;; scalar versions of the instructions as well as vector versions.
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; In order to match (*a * *b) + *c, particularly when vectorizing, allow
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;; combine to generate a multiply/add with two memory references. We then
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;; split this insn, into loading up the destination register with one of the
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;; memory operations. If we don't manage to split the insn, reload will
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;; generate the appropriate moves. The reason this is needed, is that combine
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;; has already folded one of the memory references into both the multiply and
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;; add insns, and it can't generate a new pseudo. I.e.:
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;; (set (reg1) (mem (addr1)))
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;; (set (reg2) (mult (reg1) (mem (addr2))))
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;; (set (reg3) (plus (reg2) (mem (addr3))))
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;;
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;; ??? This is historic, pre-dating the gimple fma transformation.
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;; We could now properly represent that only one memory operand is
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;; allowed and not be penalized during optimization.
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;; Intrinsic FMA operations.
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(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
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;; The standard names for fma is only available with SSE math enabled.
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(define_expand "fma<mode>4"
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@ -1743,7 +1725,7 @@
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(neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
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"(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
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;; The builtin for fma4intrin.h is not constrained by SSE math enabled.
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;; The builtin for intrinsics is not constrained by SSE math enabled.
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(define_expand "fma4i_fmadd_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand")
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(fma:FMAMODE
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@ -1752,70 +1734,137 @@
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(match_operand:FMAMODE 3 "nonimmediate_operand")))]
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"TARGET_FMA || TARGET_FMA4")
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(define_insn "*fma4i_fmadd_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
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(define_insn "*fma_fmadd_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
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(fma:FMAMODE
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
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(match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
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(match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x")))]
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"TARGET_FMA4"
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"vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssemuladd")
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x")
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(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x")))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
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vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
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vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "fma,fma,fma,fma4,fma4")
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(set_attr "type" "ssemuladd")
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(set_attr "mode" "<MODE>")])
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(define_insn "*fma4i_fmsub_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
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(define_insn "*fma_fmsub_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
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(fma:FMAMODE
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x")
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(match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x")
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(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(neg:FMAMODE
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(match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
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"TARGET_FMA4"
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"vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssemuladd")
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(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
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vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
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vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "fma,fma,fma,fma4,fma4")
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(set_attr "type" "ssemuladd")
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(set_attr "mode" "<MODE>")])
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(define_insn "*fma4i_fnmadd_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
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(define_insn "*fma_fnmadd_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
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(fma:FMAMODE
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(neg:FMAMODE
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
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(match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
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(match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x")))]
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"TARGET_FMA4"
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"vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssemuladd")
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
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(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x")))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
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vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
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vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "fma,fma,fma,fma4,fma4")
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(set_attr "type" "ssemuladd")
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(set_attr "mode" "<MODE>")])
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(define_insn "*fma4i_fnmsub_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
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(define_insn "*fma_fnmsub_<mode>"
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[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x,x,x")
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(fma:FMAMODE
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(neg:FMAMODE
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%x,x"))
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(match_operand:FMAMODE 2 "nonimmediate_operand" " x,m")
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(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x, x,x"))
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(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(neg:FMAMODE
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(match_operand:FMAMODE 3 "nonimmediate_operand" "xm,x"))))]
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"TARGET_FMA4"
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"vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssemuladd")
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(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0,xm,x"))))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfnmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
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vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
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vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "fma,fma,fma,fma4,fma4")
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(set_attr "type" "ssemuladd")
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(set_attr "mode" "<MODE>")])
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;; Scalar versions of the above. Unlike ADDSS et al, these write the
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;; entire destination register, with the high-order elements zeroed.
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;; FMA parallel floating point multiply addsub and subadd operations.
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(define_expand "fma4i_vmfmadd_<mode>"
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[(set (match_operand:VF_128 0 "register_operand")
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(vec_merge:VF_128
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(fma:VF_128
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(match_operand:VF_128 1 "nonimmediate_operand")
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(match_operand:VF_128 2 "nonimmediate_operand")
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(match_operand:VF_128 3 "nonimmediate_operand"))
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(match_dup 4)
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(const_int 1)))]
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"TARGET_FMA4"
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{
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operands[4] = CONST0_RTX (<MODE>mode);
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})
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;; It would be possible to represent these without the UNSPEC as
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;;
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;; (vec_merge
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;; (fma op1 op2 op3)
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;; (fma op1 op2 (neg op3))
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;; (merge-const))
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;;
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;; But this doesn't seem useful in practice.
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(define_expand "fmaddsub_<mode>"
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[(set (match_operand:VF 0 "register_operand")
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(unspec:VF
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[(match_operand:VF 1 "nonimmediate_operand")
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(match_operand:VF 2 "nonimmediate_operand")
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(match_operand:VF 3 "nonimmediate_operand")]
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UNSPEC_FMADDSUB))]
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"TARGET_FMA || TARGET_FMA4")
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(define_insn "*fma_fmaddsub_<mode>"
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[(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
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(unspec:VF
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[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x, x,x")
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(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x")]
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UNSPEC_FMADDSUB))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfmaddsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfmaddsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
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vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
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vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "isa" "fma,fma,fma,fma4,fma4")
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(set_attr "type" "ssemuladd")
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(set_attr "mode" "<MODE>")])
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(define_insn "*fma_fmsubadd_<mode>"
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[(set (match_operand:VF 0 "register_operand" "=x,x,x,x,x")
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(unspec:VF
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[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x, x,x")
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(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm,x,m")
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(neg:VF
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(match_operand:VF 3 "nonimmediate_operand" " x,xm,0,xm,x"))]
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UNSPEC_FMADDSUB))]
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"TARGET_FMA || TARGET_FMA4"
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"@
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vfmsubadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
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vfmsubadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
|
||||
vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}
|
||||
vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "isa" "fma,fma,fma,fma4,fma4")
|
||||
(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; FMA3 floating point scalar intrinsics. These merge result with
|
||||
;; high-order elements from the destination register.
|
||||
|
||||
(define_expand "fmai_vmfmadd_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand")
|
||||
|
|
@ -1900,6 +1949,23 @@
|
|||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; FMA4 floating point scalar intrinsics. These write the
|
||||
;; entire destination register, with the high-order elements zeroed.
|
||||
|
||||
(define_expand "fma4i_vmfmadd_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand")
|
||||
(vec_merge:VF_128
|
||||
(fma:VF_128
|
||||
(match_operand:VF_128 1 "nonimmediate_operand")
|
||||
(match_operand:VF_128 2 "nonimmediate_operand")
|
||||
(match_operand:VF_128 3 "nonimmediate_operand"))
|
||||
(match_dup 4)
|
||||
(const_int 1)))]
|
||||
"TARGET_FMA4"
|
||||
{
|
||||
operands[4] = CONST0_RTX (<MODE>mode);
|
||||
})
|
||||
|
||||
(define_insn "*fma4i_vmfmadd_<mode>"
|
||||
[(set (match_operand:VF_128 0 "register_operand" "=x,x")
|
||||
(vec_merge:VF_128
|
||||
|
|
@ -1960,152 +2026,6 @@
|
|||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; FMA4 Parallel floating point multiply addsub and subadd operations.
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
;; It would be possible to represent these without the UNSPEC as
|
||||
;;
|
||||
;; (vec_merge
|
||||
;; (fma op1 op2 op3)
|
||||
;; (fma op1 op2 (neg op3))
|
||||
;; (merge-const))
|
||||
;;
|
||||
;; But this doesn't seem useful in practice.
|
||||
|
||||
(define_expand "fmaddsub_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand")
|
||||
(match_operand:VF 2 "nonimmediate_operand")
|
||||
(match_operand:VF 3 "nonimmediate_operand")]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA || TARGET_FMA4")
|
||||
|
||||
(define_insn "*fma4_fmaddsub_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" " x,m")
|
||||
(match_operand:VF 3 "nonimmediate_operand" "xm,x")]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA4"
|
||||
"vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma4_fmsubadd_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%x,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" " x,m")
|
||||
(neg:VF
|
||||
(match_operand:VF 3 "nonimmediate_operand" "xm,x"))]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA4"
|
||||
"vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; FMA3 floating point multiply/accumulate instructions.
|
||||
;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(define_insn "*fma_fmadd_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
|
||||
(fma:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0")))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fmsub_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
|
||||
(fma:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x")
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fnmadd_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
|
||||
(fma:FMAMODE
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0")))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfnmadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfnmadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fnmsub_<mode>"
|
||||
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x,x")
|
||||
(fma:FMAMODE
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0,x"))
|
||||
(match_operand:FMAMODE 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(neg:FMAMODE
|
||||
(match_operand:FMAMODE 3 "nonimmediate_operand" " x,xm,0"))))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfnmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfnmsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfnmsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fmaddsub_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(match_operand:VF 3 "nonimmediate_operand" " x,xm,0")]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfmaddsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfmaddsub213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfmaddsub231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fma_fmsubadd_<mode>"
|
||||
[(set (match_operand:VF 0 "register_operand" "=x,x,x")
|
||||
(unspec:VF
|
||||
[(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
|
||||
(match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
|
||||
(neg:VF
|
||||
(match_operand:VF 3 "nonimmediate_operand" " x,xm,0"))]
|
||||
UNSPEC_FMADDSUB))]
|
||||
"TARGET_FMA"
|
||||
"@
|
||||
vfmsubadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
|
||||
vfmsubadd213<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
|
||||
vfmsubadd231<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssemuladd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Parallel single-precision floating point conversion operations
|
||||
|
|
@ -9619,7 +9539,7 @@
|
|||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "<sse4_1_avx2>_pblendvb"
|
||||
[(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand" "=x,x")
|
||||
[(set (match_operand:VI1_AVX2 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
|
||||
(unspec:VI1_AVX2
|
||||
[(match_operand:VI1_AVX2 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
|
||||
(match_operand:VI1_AVX2 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
|
||||
|
|
|
|||
Loading…
Reference in New Issue