2010-xx-xx Mingjie Xing <mingjie.xing@gmail.com>
gcc/testsuite/ 2010-xx-xx Mingjie Xing <mingjie.xing@gmail.com> * lib/target-supports.exp (check_effective_target_vect_int): Return true for Loongson targets. (check_effective_target_vect_shift): Likewise. (check_effective_target_vect_no_int_max): Likewise. (check_effective_target_vect_no_align): Likewise. (check_effective_target_vect_short_mult): Likewise. From-SVN: r163247
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@ -1,3 +1,12 @@
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2010-08-14 Mingjie Xing <mingjie.xing@gmail.com>
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* lib/target-supports.exp (check_effective_target_vect_int): Return
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true for Loongson targets.
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(check_effective_target_vect_shift): Likewise.
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(check_effective_target_vect_no_int_max): Likewise.
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(check_effective_target_vect_no_align): Likewise.
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(check_effective_target_vect_short_mult): Likewise.
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2010-08-14 Uros Bizjak <ubizjak@gmail.com>
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2010-08-14 Uros Bizjak <ubizjak@gmail.com>
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* g++.dg/cast.C: Change fields of structures to "long" to pass
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* g++.dg/cast.C: Change fields of structures to "long" to pass
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@ -1620,7 +1620,9 @@ proc check_effective_target_vect_int { } {
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|| [istarget sparc*-*-*]
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|| [istarget sparc*-*-*]
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|| [istarget alpha*-*-*]
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|| [istarget alpha*-*-*]
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|| [istarget ia64-*-*]
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|| [istarget ia64-*-*]
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|| [check_effective_target_arm32] } {
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|| [check_effective_target_arm32]
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|| ([istarget mips*-*-*]
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&& [check_effective_target_mips_loongson]) } {
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set et_vect_int_saved 1
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set et_vect_int_saved 1
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}
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}
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}
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}
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@ -2156,7 +2158,9 @@ proc check_effective_target_vect_shift { } {
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|| [istarget ia64-*-*]
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|| [istarget ia64-*-*]
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|| [istarget i?86-*-*]
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|| [istarget i?86-*-*]
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|| [istarget x86_64-*-*]
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|| [istarget x86_64-*-*]
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|| [check_effective_target_arm32] } {
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|| [check_effective_target_arm32]
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|| ([istarget mips*-*-*]
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&& [check_effective_target_mips_loongson]) } {
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set et_vect_shift_saved 1
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set et_vect_shift_saved 1
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}
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}
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}
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}
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@ -2270,7 +2274,9 @@ proc check_effective_target_vect_no_int_max { } {
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set et_vect_no_int_max_saved 0
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set et_vect_no_int_max_saved 0
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if { [istarget sparc*-*-*]
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if { [istarget sparc*-*-*]
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|| [istarget spu-*-*]
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|| [istarget spu-*-*]
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|| [istarget alpha*-*-*] } {
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|| [istarget alpha*-*-*]
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|| ([istarget mips*-*-*]
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&& [check_effective_target_mips_loongson]) } {
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set et_vect_no_int_max_saved 1
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set et_vect_no_int_max_saved 1
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}
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}
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}
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}
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@ -2643,7 +2649,9 @@ proc check_effective_target_vect_no_align { } {
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if { [istarget mipsisa64*-*-*]
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if { [istarget mipsisa64*-*-*]
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|| [istarget sparc*-*-*]
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|| [istarget sparc*-*-*]
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|| [istarget ia64-*-*]
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|| [istarget ia64-*-*]
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|| [check_effective_target_arm32] } {
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|| [check_effective_target_arm32]
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|| ([istarget mips*-*-*]
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&& [check_effective_target_mips_loongson]) } {
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set et_vect_no_align_saved 1
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set et_vect_no_align_saved 1
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}
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}
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}
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}
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@ -2833,8 +2841,10 @@ proc check_effective_target_vect_short_mult { } {
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|| [istarget spu-*-*]
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|| [istarget spu-*-*]
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|| [istarget i?86-*-*]
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|| [istarget i?86-*-*]
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|| [istarget x86_64-*-*]
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|| [istarget x86_64-*-*]
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|| [istarget powerpc*-*-*]
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|| [istarget powerpc*-*-*]
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|| [check_effective_target_arm32] } {
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|| [check_effective_target_arm32]
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|| ([istarget mips*-*-*]
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&& [check_effective_target_mips_loongson]) } {
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set et_vect_short_mult_saved 1
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set et_vect_short_mult_saved 1
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}
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}
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}
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}
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