Refine movhfcc.
For AVX512-FP16, HFmode only supports vcmpsh whose dest is mask
register, so for movhfcc, it's
vcmpsh op2, op1, %k1
vmovsh op1, op2{%k1}
mov op2, dest
gcc/ChangeLog:
PR target/102639
* config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Handle
HFmode.
(ix86_use_mask_cmp_p): Ditto.
(ix86_expand_sse_movcc): Ditto.
* config/i386/i386.md (setcc_hf_mask): New define_insn.
(movhf_mask): Ditto.
(UNSPEC_MOVCC_MASK): New unspec.
* config/i386/sse.md (UNSPEC_PCMP): Move to i386.md.
gcc/testsuite/ChangeLog:
* g++.target/i386/pr102639.C: New test.
This commit is contained in:
liuhongt
parent
ce6eec3926
commit
0d788c358b
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@ -3613,6 +3613,10 @@ ix86_valid_mask_cmp_mode (machine_mode mode)
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if (TARGET_XOP && !TARGET_AVX512F)
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return false;
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/* HFmode only supports vcmpsh whose dest is mask register. */
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if (TARGET_AVX512FP16 && mode == HFmode)
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return true;
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/* AVX512F is needed for mask operation. */
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if (!(TARGET_AVX512F && VECTOR_MODE_P (mode)))
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return false;
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@ -3634,7 +3638,9 @@ ix86_use_mask_cmp_p (machine_mode mode, machine_mode cmp_mode,
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{
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int vector_size = GET_MODE_SIZE (mode);
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if (vector_size < 16)
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if (cmp_mode == HFmode)
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return true;
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else if (vector_size < 16)
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return false;
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else if (vector_size == 64)
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return true;
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@ -3750,7 +3756,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
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&& GET_MODE_CLASS (cmpmode) == MODE_INT)
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{
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gcc_assert (ix86_valid_mask_cmp_mode (mode));
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/* Using vector move with mask register. */
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/* Using scalar/vector move with mask register. */
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cmp = force_reg (cmpmode, cmp);
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/* Optimize for mask zero. */
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op_true = (op_true != CONST0_RTX (mode)
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@ -3769,8 +3775,13 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
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std::swap (op_true, op_false);
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}
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rtx vec_merge = gen_rtx_VEC_MERGE (mode, op_true, op_false, cmp);
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emit_insn (gen_rtx_SET (dest, vec_merge));
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if (mode == HFmode)
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emit_insn (gen_movhf_mask (dest, op_true, op_false, cmp));
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else
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{
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rtx vec_merge = gen_rtx_VEC_MERGE (mode, op_true, op_false, cmp);
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emit_insn (gen_rtx_SET (dest, vec_merge));
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}
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return;
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}
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else if (vector_all_ones_operand (op_true, mode)
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@ -117,6 +117,7 @@
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;; For SSE/MMX support:
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UNSPEC_FIX_NOTRUNC
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UNSPEC_MASKMOV
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UNSPEC_MOVCC_MASK
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UNSPEC_MOVMSK
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UNSPEC_BLENDV
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UNSPEC_PSHUFB
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@ -125,8 +126,9 @@
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UNSPEC_RSQRT
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UNSPEC_PSADBW
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;; For AVX512F support
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;; For AVX/AVX512F support
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UNSPEC_SCALEF
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UNSPEC_PCMP
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;; Generic math support
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UNSPEC_IEEE_MIN ; not commutative
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@ -13608,6 +13610,20 @@
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "setcc_hf_mask"
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[(set (match_operand:QI 0 "register_operand" "=k")
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(unspec:QI
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[(match_operand:HF 1 "register_operand" "v")
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(match_operand:HF 2 "nonimmediate_operand" "vm")
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(match_operand:SI 3 "const_0_to_31_operand" "n")]
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UNSPEC_PCMP))]
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"TARGET_AVX512FP16"
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"vcmpsh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "prefix" "evex")
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(set_attr "mode" "HF")])
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;; Basic conditional jump instructions.
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@ -19841,6 +19857,22 @@
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operands[9] = replace_rtx (operands[6], operands[0], operands[1], true);
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})
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(define_insn "movhf_mask"
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[(set (match_operand:HF 0 "nonimmediate_operand" "=v,m,v")
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(unspec:HF
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[(match_operand:HF 1 "nonimmediate_operand" "m,v,v")
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(match_operand:HF 2 "nonimm_or_0_operand" "0C,0C,0C")
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(match_operand:QI 3 "register_operand" "Yk,Yk,Yk")]
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UNSPEC_MOVCC_MASK))]
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"TARGET_AVX512FP16"
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"@
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vmovsh\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}
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vmovsh\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}
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vmovsh\t{%d1, %0%{%3%}%N2|%0%{%3%}%N2, %d1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "evex")
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(set_attr "mode" "HF")])
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(define_expand "movhfcc"
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[(set (match_operand:HF 0 "register_operand")
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(if_then_else:HF
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@ -67,7 +67,6 @@
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UNSPEC_PCLMUL
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;; For AVX support
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UNSPEC_PCMP
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UNSPEC_VPERMIL
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UNSPEC_VPERMIL2
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UNSPEC_VPERMIL2F128
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@ -0,0 +1,19 @@
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/* PR target/102639 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -std=c++14 -mavx512fp16" } */
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/* { dg-final { scan-assembler-times "vminsh" 1 } } */
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typedef _Float16 v16hf __attribute__((vector_size(2)));
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v16hf vcond_v16hfv16hfge_b, vcond_v16hfv16hfge_c, vcond_v16hfv16hfge_d,
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__attribute__vcond_v16hfv16hfge_a;
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v16hf __attribute__vcond_v16hfv16hfge() {
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return __attribute__vcond_v16hfv16hfge_a >= vcond_v16hfv16hfge_b
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? vcond_v16hfv16hfge_c
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: vcond_v16hfv16hfge_d;
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}
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v16hf __attribute__vcond_v16hfv16hfmax() {
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return __attribute__vcond_v16hfv16hfge_a < vcond_v16hfv16hfge_b
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? __attribute__vcond_v16hfv16hfge_a
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: vcond_v16hfv16hfge_b;
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}
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