sparc.c (sparc_absnegfloat_split_legitimate): Do not call alter_subreg.
* sparc.c (sparc_absnegfloat_split_legitimate): Do not call alter_subreg. * sparc.md (post-reload splitters): Do not call alter_subreg. * cfgrtl.c (purge_dead_edges): Fix typo in previous fix. From-SVN: r47339
This commit is contained in:
parent
78b583fed8
commit
0e1638d4c3
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@ -1,3 +1,10 @@
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Mon Nov 26 11:36:20 CET 2001 Jan Hubicka <jh@suse.cz>
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* sparc.c (sparc_absnegfloat_split_legitimate): Do not call
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alter_subreg.
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* sparc.md (post-reload splitters): Do not call alter_subreg.
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* cfgrtl.c (purge_dead_edges): Fix typo in previous fix.
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2001-11-25 Aldy Hernandez <aldyh@redhat.com>
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* regclass.c (choose_hard_reg_mode): Handle vector arguments.
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@ -1841,7 +1841,7 @@ purge_dead_edges (bb)
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/* Avoid abnormal flags to leak from computed jumps turned
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into simplejumps. */
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e->flags &= EDGE_ABNORMAL;
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e->flags &= ~EDGE_ABNORMAL;
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/* Check purposes we can have edge. */
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if ((e->flags & EDGE_FALLTHRU)
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@ -5605,12 +5605,8 @@ int
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sparc_absnegfloat_split_legitimate (x, y)
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rtx x, y;
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{
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if (GET_CODE (x) == SUBREG)
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x = alter_subreg (x);
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if (GET_CODE (x) != REG)
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return 0;
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if (GET_CODE (y) == SUBREG)
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y = alter_subreg (y);
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if (GET_CODE (y) != REG)
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return 0;
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if (REGNO (x) == REGNO (y))
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@ -2798,11 +2798,6 @@
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rtx dest1, dest2;
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rtx src1, src2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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dest1 = gen_highpart (SImode, set_dest);
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dest2 = gen_lowpart (SImode, set_dest);
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src1 = gen_highpart (SImode, set_src);
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@ -3366,8 +3361,6 @@
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REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
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REAL_VALUE_TO_TARGET_DOUBLE (r, l);
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
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if (TARGET_ARCH64)
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@ -3430,11 +3423,6 @@
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rtx dest1, dest2;
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rtx src1, src2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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dest1 = gen_highpart (SFmode, set_dest);
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dest2 = gen_lowpart (SFmode, set_dest);
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src1 = gen_highpart (SFmode, set_src);
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@ -3469,9 +3457,6 @@
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rtx word0 = adjust_address (operands[1], SFmode, 0);
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rtx word1 = adjust_address (operands[1], SFmode, 4);
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
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{
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emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
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@ -3503,8 +3488,6 @@
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rtx word0 = adjust_address (operands[0], SFmode, 0);
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rtx word1 = adjust_address (operands[0], SFmode, 4);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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emit_insn (gen_movsf (word0,
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gen_highpart (SFmode, operands[1])));
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emit_insn (gen_movsf (word1,
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@ -3549,8 +3532,6 @@
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rtx set_dest = operands[0];
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rtx dest1, dest2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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dest1 = gen_highpart (SFmode, set_dest);
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dest2 = gen_lowpart (SFmode, set_dest);
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emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
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@ -3754,11 +3735,6 @@
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rtx dest1, dest2;
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rtx src1, src2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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src1 = gen_df_reg (set_src, 0);
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@ -3791,9 +3767,6 @@
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switch (GET_CODE (set_dest))
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{
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case SUBREG:
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set_dest = alter_subreg (set_dest);
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/* FALLTHROUGH */
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case REG:
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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@ -3824,8 +3797,6 @@
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rtx set_dest, dest1, dest2;
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set_dest = operands[0];
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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@ -3855,8 +3826,6 @@
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"
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{
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rtx set_src = operands[1];
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if (GET_CODE (set_src) == SUBREG)
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set_src = alter_subreg (set_src);
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emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
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gen_df_reg (set_src, 0)));
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@ -4214,13 +4183,6 @@
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rtx dest1, dest2;
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rtx srca1, srca2, srcb1, srcb2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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if (GET_CODE (set_srca) == SUBREG)
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set_srca = alter_subreg (set_srca);
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if (GET_CODE (set_srcb) == SUBREG)
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set_srcb = alter_subreg (set_srcb);
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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srca1 = gen_df_reg (set_srca, 0);
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@ -4379,13 +4341,6 @@
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rtx dest1, dest2;
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rtx srca1, srca2, srcb1, srcb2;
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if (GET_CODE (set_dest) == SUBREG)
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set_dest = alter_subreg (set_dest);
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if (GET_CODE (set_srca) == SUBREG)
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set_srca = alter_subreg (set_srca);
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if (GET_CODE (set_srcb) == SUBREG)
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set_srcb = alter_subreg (set_srcb);
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dest1 = gen_df_reg (set_dest, 0);
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dest2 = gen_df_reg (set_dest, 1);
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srca1 = gen_df_reg (set_srca, 0);
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@ -4558,9 +4513,6 @@
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{
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rtx dest1, dest2;
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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dest1 = gen_highpart (SImode, operands[0]);
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dest2 = gen_lowpart (SImode, operands[0]);
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@ -6617,8 +6569,6 @@
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(set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
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"
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{
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[4] = gen_highpart (SImode, operands[0]);
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operands[5] = gen_lowpart (SImode, operands[0]);
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operands[6] = gen_highpart (SImode, operands[2]);
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@ -6662,9 +6612,7 @@
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
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(set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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"operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -6772,9 +6720,7 @@
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
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(set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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"operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -6907,9 +6853,7 @@
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
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(set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[3] = gen_highpart (SImode, operands[0]);
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"operands[3] = gen_highpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_highpart (SImode, operands[2]);
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operands[6] = gen_lowpart (SImode, operands[0]);
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@ -7209,9 +7153,7 @@
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&& REGNO (SUBREG_REG (operands[0])) < 32))"
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[(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
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(set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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operands[2] = gen_highpart (SImode, operands[0]);
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"operands[2] = gen_highpart (SImode, operands[0]);
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operands[3] = gen_highpart (SImode, operands[1]);
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operands[4] = gen_lowpart (SImode, operands[0]);
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operands[5] = gen_lowpart (SImode, operands[1]);")
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@ -7587,11 +7529,7 @@
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[(set (match_dup 2) (neg:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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@ -7619,11 +7557,7 @@
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
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[(set (match_dup 2) (neg:DF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
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operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
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@ -7653,11 +7587,7 @@
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
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[(set (match_dup 2) (neg:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
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@ -7704,11 +7634,7 @@
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[(set (match_dup 2) (abs:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))
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(set (match_dup 6) (match_dup 7))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
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@ -7745,11 +7671,7 @@
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
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[(set (match_dup 2) (abs:DF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
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operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
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@ -7779,11 +7701,7 @@
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&& sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
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[(set (match_dup 2) (abs:SF (match_dup 3)))
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(set (match_dup 4) (match_dup 5))]
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"if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = alter_subreg (operands[1]);
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operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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"operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
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operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
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operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
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operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
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