[ARC] Code size modifications.
gcc/ 2017-03-13 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_init): Use multiplier whenever we have it. (arc_conditional_register_usage): Use a different allocation order when optimizing for size. * common/config/arc/arc-common.c (arc_option_optimization_table): Section anchors default on when optimizing for size. From-SVN: r246091
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@ -1,3 +1,11 @@
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2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
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(arc_conditional_register_usage): Use a different allocation order
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when optimizing for size.
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* common/config/arc/arc-common.c (arc_option_optimization_table):
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Section anchors default on when optimizing for size.
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2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.md (*tst_bitfield_tst): Fix pattern.
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@ -46,6 +46,7 @@ arc_option_init_struct (struct gcc_options *opts)
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#define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
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static const struct default_options arc_option_optimization_table[] =
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{
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{ OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
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{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
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{ OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 },
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{ OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 },
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@ -676,6 +676,12 @@ make_pass_arc_predicate_delay_insns (gcc::context *ctxt)
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static void
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arc_init (void)
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{
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if (TARGET_V2)
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{
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/* I have the multiplier, then use it*/
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if (TARGET_MPYW || TARGET_MULTI)
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arc_multcost = COSTS_N_INSNS (1);
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}
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/* Note: arc_multcost is only used in rtx_cost if speed is true. */
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if (arc_multcost < 0)
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switch (arc_tune)
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@ -1374,20 +1380,42 @@ arc_conditional_register_usage (void)
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}
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if (TARGET_Q_CLASS)
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{
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reg_alloc_order[2] = 12;
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reg_alloc_order[3] = 13;
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reg_alloc_order[4] = 14;
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reg_alloc_order[5] = 15;
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reg_alloc_order[6] = 1;
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reg_alloc_order[7] = 0;
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reg_alloc_order[8] = 4;
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reg_alloc_order[9] = 5;
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reg_alloc_order[10] = 6;
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reg_alloc_order[11] = 7;
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reg_alloc_order[12] = 8;
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reg_alloc_order[13] = 9;
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reg_alloc_order[14] = 10;
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reg_alloc_order[15] = 11;
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if (optimize_size)
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{
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reg_alloc_order[0] = 0;
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reg_alloc_order[1] = 1;
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reg_alloc_order[2] = 2;
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reg_alloc_order[3] = 3;
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reg_alloc_order[4] = 12;
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reg_alloc_order[5] = 13;
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reg_alloc_order[6] = 14;
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reg_alloc_order[7] = 15;
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reg_alloc_order[8] = 4;
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reg_alloc_order[9] = 5;
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reg_alloc_order[10] = 6;
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reg_alloc_order[11] = 7;
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reg_alloc_order[12] = 8;
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reg_alloc_order[13] = 9;
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reg_alloc_order[14] = 10;
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reg_alloc_order[15] = 11;
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}
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else
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{
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reg_alloc_order[2] = 12;
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reg_alloc_order[3] = 13;
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reg_alloc_order[4] = 14;
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reg_alloc_order[5] = 15;
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reg_alloc_order[6] = 1;
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reg_alloc_order[7] = 0;
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reg_alloc_order[8] = 4;
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reg_alloc_order[9] = 5;
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reg_alloc_order[10] = 6;
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reg_alloc_order[11] = 7;
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reg_alloc_order[12] = 8;
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reg_alloc_order[13] = 9;
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reg_alloc_order[14] = 10;
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reg_alloc_order[15] = 11;
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}
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}
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if (TARGET_SIMD_SET)
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{
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