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re PR tree-optimization/29777 (missed optimization: model missing widen_mult* idioms for SSE) 

PR target/29777
	* config/i386/sse.md (smulv8hi3_highpart): Change from define_insn
	to define_expand.
	(umulv8hi3_highpart): Ditto.
	(vec_widen_smult_hi_v8hi): New expander.
	(vec_widen_smult_lo_v8hi): Ditto.

testsuite/ChangeLog:

	PR target/29777
        * lib/target-supports.exp (vect_widen_mult_hi_to_si): Add i?86-*-*
	and x86_64-*-* targets.

From-SVN: r118649
This commit is contained in:
Uros Bizjak 2006-11-10 09:45:47 +01:00 committed by Uros Bizjak
parent e61e5ddcce
commit 0e9dac9e16
4 changed files with 60 additions and 3 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2006-11-10 Uros Bizjak <ubizjak@gmail.com>
PR target/29777
* config/i386/sse.md (smulv8hi3_highpart): Change from define_insn
to define_expand.
(umulv8hi3_highpart): Ditto.
(vec_widen_smult_hi_v8hi): New expander.
(vec_widen_smult_lo_v8hi): Ditto.
2006-11-09 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* builtins.c (do_mpfr_arg3): New.

44
gcc/config/i386/sse.md
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@ -2620,7 +2620,7 @@
[(set_attr "type" "sseimul")
(set_attr "mode" "TI")])
(define_insn "smulv8hi3_highpart"
(define_expand "smulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "")
(truncate:V8HI
(lshiftrt:V8SI
@ -2648,7 +2648,7 @@
[(set_attr "type" "sseimul")
(set_attr "mode" "TI")])
(define_insn "umulv8hi3_highpart"
(define_expand "umulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "")
(truncate:V8HI
(lshiftrt:V8SI
@ -2818,6 +2818,46 @@
DONE;
})
(define_expand "vec_widen_smult_hi_v8hi"
[(match_operand:V4SI 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "register_operand" "")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2, dest;
op1 = operands[1];
op2 = operands[2];
t1 = gen_reg_rtx (V8HImode);
t2 = gen_reg_rtx (V8HImode);
dest = gen_lowpart (V8HImode, operands[0]);
emit_insn (gen_mulv8hi3 (t1, op1, op2));
emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
DONE;
})
(define_expand "vec_widen_smult_lo_v8hi"
[(match_operand:V4SI 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "register_operand" "")]
"TARGET_SSE2"
{
rtx op1, op2, t1, t2, dest;
op1 = operands[1];
op2 = operands[2];
t1 = gen_reg_rtx (V8HImode);
t2 = gen_reg_rtx (V8HImode);
dest = gen_lowpart (V8HImode, operands[0]);
emit_insn (gen_mulv8hi3 (t1, op1, op2));
emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
DONE;
})
(define_expand "vec_widen_umult_hi_v8hi"
[(match_operand:V4SI 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2006-11-10 Uros Bizjak <ubizjak@gmail.com>
PR target/29777
* lib/target-supports.exp (vect_widen_mult_hi_to_si): Add i?86-*-*
and x86_64-*-* targets.
2006-11-09 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* gcc.dg/torture/builtin-math-2.c: Test builtin fma.

4
gcc/testsuite/lib/target-supports.exp
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@ -1603,7 +1603,9 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } {
} else {
set et_vect_widen_mult_hi_to_si_saved 0
}
if { [istarget powerpc*-*-*] } {
if { [istarget powerpc*-*-*]
|| [istarget i?86-*-*]
|| [istarget x86_64-*-*] } {
set et_vect_widen_mult_hi_to_si_saved 1
}
}