i386.md (pushsi, [...]): Disable.
* i386.md (pushsi, pushsi2_prologue): Disable. (pushsi2_rex64): New. (movabs?i_1_rex64, movabs?i_2_rex64): New. (movqi_ext_1): Disable for 64bit. (movqi_ext_1_rex64): New. (pushdi2_rex64): New pattern, peep2s and splitter. (pushdi2_prologue_rex64): New pattern. (popdi1_epilogue_rex64, popdi1, movdi_xor_rex64, movdi_or_rex64): Likewise. (movdi splitters): Disable for 64bit. (movdi_1_rex64): New pattern, peep2s and splitters. (swapdi): New pattern. (pushsf): Disable for 64bit. (pushsf_rex64): New pattern and splitter. (pushdf_nointeger): Disable for 64bit. (pushdf_integer): Handle the 64bit case. (pushtf): Likewise; update splitters. From-SVN: r40758
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
ee402fc993
commit
0ec259edcd
@ -1,3 +1,23 @@
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Thu Mar 22 21:41:16 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (pushsi, pushsi2_prologue): Disable.
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(pushsi2_rex64): New.
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(movabs?i_1_rex64, movabs?i_2_rex64): New.
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(movqi_ext_1): Disable for 64bit.
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(movqi_ext_1_rex64): New.
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(pushdi2_rex64): New pattern, peep2s and splitter.
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(pushdi2_prologue_rex64): New pattern.
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(popdi1_epilogue_rex64, popdi1, movdi_xor_rex64, movdi_or_rex64):
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Likewise.
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(movdi splitters): Disable for 64bit.
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(movdi_1_rex64): New pattern, peep2s and splitters.
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(swapdi): New pattern.
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(pushsf): Disable for 64bit.
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(pushsf_rex64): New pattern and splitter.
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(pushdf_nointeger): Disable for 64bit.
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(pushdf_integer): Handle the 64bit case.
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(pushtf): Likewise; update splitters.
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2001-03-22 Richard Henderson <rth@redhat.com>
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* mkconfig.sh: Include insn-flags.h.
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@ -1622,16 +1622,25 @@
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(define_insn "*pushsi2"
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[(set (match_operand:SI 0 "push_operand" "=<")
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(match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
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""
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"!TARGET_64BIT"
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"push{l}\\t%1"
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[(set_attr "type" "push")
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(set_attr "mode" "SI")])
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;; For 64BIT abi we always round up to 8 bytes.
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(define_insn "*pushsi2_rex64"
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[(set (match_operand:SI 0 "push_operand" "=X")
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(match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
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"TARGET_64BIT"
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"push{q}\\t%q1"
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[(set_attr "type" "push")
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(set_attr "mode" "SI")])
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(define_insn "*pushsi2_prologue"
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[(set (match_operand:SI 0 "push_operand" "=<")
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(match_operand:SI 1 "general_no_elim_operand" "ri*m"))
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(set (reg:SI 6) (reg:SI 6))]
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""
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"!TARGET_64BIT"
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"push{l}\\t%1"
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[(set_attr "type" "push")
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(set_attr "mode" "SI")])
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@ -1715,6 +1724,38 @@
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(set_attr "modrm" "0,*,0,*,*,*")
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(set_attr "mode" "SI")])
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;; Stores and loads of ax to arbitary constant address.
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;; We fake an second form of instruction to force reload to load address
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;; into register when rax is not available
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(define_insn "*movabssi_1_rex64"
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[(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
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(match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
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"TARGET_64BIT"
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"@
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movabs{l}\\t{%1, %P0|%P0, %1}
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mov{l}\\t{%1, %a0|%a0, %1}
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movabs{l}\\t{%1, %a0|%a0, %1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*,*")
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(set_attr "length_address" "8,0,0")
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(set_attr "length_immediate" "0,*,*")
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(set_attr "memory" "store")
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(set_attr "mode" "SI")])
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(define_insn "*movabssi_2_rex64"
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[(set (match_operand:SI 0 "register_operand" "=a,r")
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(mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
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"TARGET_64BIT"
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"@
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movabs{l}\\t{%P1, %0|%0, %P1}
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mov{l}\\t{%a1, %0|%0, %a1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*")
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(set_attr "length_address" "8,0")
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(set_attr "length_immediate" "0")
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(set_attr "memory" "load")
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(set_attr "mode" "SI")])
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(define_insn "*swapsi"
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[(set (match_operand:SI 0 "register_operand" "+r")
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(match_operand:SI 1 "register_operand" "+r"))
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@ -1796,6 +1837,38 @@
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(const_string "HI")))
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(set_attr "modrm" "0,*,*,0,*,*")])
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;; Stores and loads of ax to arbitary constant address.
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;; We fake an second form of instruction to force reload to load address
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;; into register when rax is not available
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(define_insn "*movabshi_1_rex64"
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[(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
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(match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
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"TARGET_64BIT"
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"@
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movabs{w}\\t{%1, %P0|%P0, %1}
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mov{w}\\t{%1, %a0|%a0, %1}
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movabs{w}\\t{%1, %a0|%a0, %1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*,*")
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(set_attr "length_address" "8,0,0")
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(set_attr "length_immediate" "0,*,*")
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(set_attr "memory" "store")
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(set_attr "mode" "HI")])
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(define_insn "*movabshi_2_rex64"
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[(set (match_operand:HI 0 "register_operand" "=a,r")
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(mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
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"TARGET_64BIT"
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"@
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movabs{w}\\t{%P1, %0|%0, %P1}
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mov{w}\\t{%a1, %0|%0, %a1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*")
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(set_attr "length_address" "8,0")
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(set_attr "length_immediate" "0")
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(set_attr "memory" "load")
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(set_attr "mode" "HI")])
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(define_insn "*swaphi_1"
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[(set (match_operand:HI 0 "register_operand" "+r")
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(match_operand:HI 1 "register_operand" "+r"))
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@ -2024,11 +2097,11 @@
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(set_attr "mode" "SI")])
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(define_insn "*movqi_extv_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
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(sign_extract:QI (match_operand:SI 1 "register_operand" "q,q")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
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(sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)))]
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""
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"!TARGET_64BIT"
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"*
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{
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switch (get_attr_type (insn))
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@ -2051,6 +2124,66 @@
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(const_string "SI")
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(const_string "QI")))])
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(define_insn "*movqi_extv_1_rex64"
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[(set (match_operand:QI 0 "register_operand" "=Q,?R")
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(sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)))]
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"TARGET_64BIT"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_IMOVX:
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return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
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default:
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return \"mov{b}\\t{%h1, %0|%0, %h1}\";
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}
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}"
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[(set (attr "type")
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(if_then_else (and (match_operand:QI 0 "register_operand" "")
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(ior (not (match_operand:QI 0 "q_regs_operand" ""))
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(ne (symbol_ref "TARGET_MOVX")
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(const_int 0))))
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(const_string "imovx")
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(const_string "imov")))
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(set (attr "mode")
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(if_then_else (eq_attr "type" "imovx")
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(const_string "SI")
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(const_string "QI")))])
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;; Stores and loads of ax to arbitary constant address.
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;; We fake an second form of instruction to force reload to load address
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;; into register when rax is not available
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(define_insn "*movabsqi_1_rex64"
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[(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
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(match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
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"TARGET_64BIT"
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"@
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movabs{q}\\t{%1, %P0|%P0, %1}
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mov{q}\\t{%1, %a0|%a0, %1}
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movabs{q}\\t{%1, %a0|%a0, %1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*,*")
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(set_attr "length_address" "8,0,0")
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(set_attr "length_immediate" "0,*,*")
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(set_attr "memory" "store")
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(set_attr "mode" "QI")])
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(define_insn "*movabsqi_2_rex64"
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[(set (match_operand:QI 0 "register_operand" "=a,r")
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(mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
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"TARGET_64BIT"
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"@
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movabs{q}\\t{%P1, %0|%0, %P1}
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mov{q}\\t{%a1, %0|%0, %a1}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0,*")
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(set_attr "length_address" "8,0")
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(set_attr "length_immediate" "0")
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(set_attr "memory" "load")
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(set_attr "mode" "QI")])
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(define_insn "*movsi_extzv_1"
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[(set (match_operand:SI 0 "register_operand" "=R")
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
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@ -2160,6 +2293,117 @@
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"!TARGET_64BIT"
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"#")
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(define_insn "pushdi2_rex64"
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[(set (match_operand:DI 0 "push_operand" "=<,!<")
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(match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
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"TARGET_64BIT"
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"@
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push{q}\\t%1
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#"
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[(set_attr "type" "push,multi")
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(set_attr "mode" "DI")])
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;; Convert impossible pushes of immediate to existing instructions.
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;; First try to get scratch register and go trought it. In case this
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;; fails, push sign extended lower part first and then overwrite
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;; upper part by 32bit move.
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(define_peephole2
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[(match_scratch:DI 2 "r")
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(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "immediate_operand" ""))]
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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;; We need to define this as both peepholer and splitter for case
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;; peephole2 pass is not run.
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(define_peephole2
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[(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "immediate_operand" ""))]
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode) && 1"
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))]
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"split_di (operands + 1, 1, operands + 2, operands + 3);
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operands[1] = gen_lowpart (DImode, operands[2]);
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operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
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GEN_INT (4)));
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")
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(define_split
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[(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "immediate_operand" ""))]
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"TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
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&& !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))]
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"split_di (operands + 1, 1, operands + 2, operands + 3);
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operands[1] = gen_lowpart (DImode, operands[2]);
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operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
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GEN_INT (4)));
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")
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(define_insn "*pushdi2_prologue_rex64"
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[(set (match_operand:DI 0 "push_operand" "=<")
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(match_operand:DI 1 "general_no_elim_operand" "re*m"))
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(set (reg:DI 6) (reg:DI 6))]
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"TARGET_64BIT"
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"push{q}\\t%1"
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[(set_attr "type" "push")
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(set_attr "mode" "DI")])
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(define_insn "*popdi1_epilogue_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
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(mem:DI (reg:DI 7)))
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(set (reg:DI 7)
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(plus:DI (reg:DI 7) (const_int 8)))
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(set (reg:DI 6) (reg:DI 6))]
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"TARGET_64BIT"
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"pop{q}\\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "DI")])
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(define_insn "popdi1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
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(mem:DI (reg:DI 7)))
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(set (reg:DI 7)
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(plus:DI (reg:DI 7) (const_int 8)))]
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"TARGET_64BIT"
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"pop{q}\\t%0"
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[(set_attr "type" "pop")
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(set_attr "mode" "DI")])
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(define_insn "*movdi_xor_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "const0_operand" "i"))
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(clobber (reg:CC 17))]
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"reload_completed && (!TARGET_USE_MOV0 || optimize_size)
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&& TARGET_64BIT"
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"xor{l}\\t{%k0, %k0|%k0, %k0}"
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[(set_attr "type" "alu1")
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(set_attr "mode" "SI")
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(set_attr "length_immediate" "0")])
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(define_insn "*movdi_or_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operand:DI 1 "const_int_operand" "i"))
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(clobber (reg:CC 17))]
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"reload_completed && GET_CODE (operands[1]) == CONST_INT
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&& TARGET_64BIT
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&& INTVAL (operands[1]) == -1
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&& (TARGET_PENTIUM || optimize_size)"
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"*
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{
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operands[1] = constm1_rtx;
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return \"or{q}\\t{%1, %0|%0, %1}\";
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}"
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[(set_attr "type" "alu1")
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(set_attr "mode" "DI")
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(set_attr "length_immediate" "1")])
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(define_insn "*movdi_2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
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(match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
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@ -2175,7 +2419,7 @@
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(define_split
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[(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "general_operand" ""))]
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"reload_completed && ! MMX_REG_P (operands[1]) && !TARGET_64BIT"
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"!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[1])"
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[(const_int 0)]
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"if (!ix86_split_long_move (operands)) abort (); DONE;")
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@ -2183,10 +2427,135 @@
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(define_split
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(match_operand:DI 1 "general_operand" ""))]
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"reload_completed && ! MMX_REG_P (operands[0]) && ! MMX_REG_P (operands[1])"
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"!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[0])
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&& ! MMX_REG_P (operands[1])"
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[(set (match_dup 2) (match_dup 5))
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(set (match_dup 3) (match_dup 6))]
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"if (ix86_split_long_move (operands)) DONE;")
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(define_insn "*movdi_1_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,*m,*Y")
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(match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*m"))]
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"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
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&& TARGET_64BIT"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_SSE:
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case TYPE_MMX:
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return \"movd\\t{%1, %0|%0, %1}\";
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case TYPE_MULTI:
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return \"#\";
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case TYPE_LEA:
|
||||
return \"lea{q}\\t{%a1, %0|%0, %a1}\";
|
||||
default:
|
||||
if (flag_pic && SYMBOLIC_CONST (operands[1]))
|
||||
abort ();
|
||||
if (get_attr_mode (insn) == MODE_SI)
|
||||
return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
|
||||
else if (which_alternative == 2)
|
||||
return \"movabs{q}\\t{%1, %0|%0, %1}\";
|
||||
else
|
||||
return \"mov{q}\\t{%1, %0|%0, %1}\";
|
||||
}
|
||||
}"
|
||||
[(set (attr "type")
|
||||
(cond [(eq_attr "alternative" "5,6")
|
||||
(const_string "mmx")
|
||||
(eq_attr "alternative" "7,8")
|
||||
(const_string "sse")
|
||||
(eq_attr "alternative" "4")
|
||||
(const_string "multi")
|
||||
(and (ne (symbol_ref "flag_pic") (const_int 0))
|
||||
(match_operand:DI 1 "symbolic_operand" ""))
|
||||
(const_string "lea")
|
||||
]
|
||||
(const_string "imov")))
|
||||
(set_attr "modrm" "*,0,0,*,*,*,*,*,*")
|
||||
(set_attr "length_immediate" "*,4,8,*,*,*,*,*,*")
|
||||
(set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI")])
|
||||
|
||||
;; Stores and loads of ax to arbitary constant address.
|
||||
;; We fake an second form of instruction to force reload to load address
|
||||
;; into register when rax is not available
|
||||
(define_insn "*movabsdi_1_rex64"
|
||||
[(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
|
||||
(match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
movabs{q}\\t{%1, %P0|%P0, %1}
|
||||
mov{q}\\t{%1, %a0|%a0, %1}
|
||||
movabs{q}\\t{%1, %a0|%a0, %1}"
|
||||
[(set_attr "type" "imov")
|
||||
(set_attr "modrm" "0,*,*")
|
||||
(set_attr "length_address" "8,0,0")
|
||||
(set_attr "length_immediate" "0,*,*")
|
||||
(set_attr "memory" "store")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "*movabsdi_2_rex64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a,r")
|
||||
(mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
movabs{q}\\t{%P1, %0|%0, %P1}
|
||||
mov{q}\\t{%a1, %0|%0, %a1}"
|
||||
[(set_attr "type" "imov")
|
||||
(set_attr "modrm" "0,*")
|
||||
(set_attr "length_address" "8,0")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set_attr "memory" "load")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
;; Convert impossible stores of immediate to existing instructions.
|
||||
;; First try to get scratch register and go trought it. In case this
|
||||
;; fails, move by 32bit parts.
|
||||
(define_peephole2
|
||||
[(match_scratch:DI 2 "r")
|
||||
(set (match_operand:DI 0 "memory_operand" "")
|
||||
(match_operand:DI 1 "immediate_operand" ""))]
|
||||
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
|
||||
&& !x86_64_immediate_operand (operands[1], DImode)"
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(set (match_dup 0) (match_dup 2))]
|
||||
"")
|
||||
|
||||
;; We need to define this as both peepholer and splitter for case
|
||||
;; peephole2 pass is not run.
|
||||
(define_peephole2
|
||||
[(set (match_operand:DI 0 "memory_operand" "")
|
||||
(match_operand:DI 1 "immediate_operand" ""))]
|
||||
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
|
||||
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
|
||||
[(set (match_dup 2) (match_dup 3))
|
||||
(set (match_dup 4) (match_dup 5))]
|
||||
"split_di (operands, 2, operands + 2, operands + 4);")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "memory_operand" "")
|
||||
(match_operand:DI 1 "immediate_operand" ""))]
|
||||
"TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
|
||||
&& !symbolic_operand (operands[1], DImode)
|
||||
&& !x86_64_immediate_operand (operands[1], DImode)"
|
||||
[(set (match_dup 2) (match_dup 3))
|
||||
(set (match_dup 4) (match_dup 5))]
|
||||
"split_di (operands, 2, operands + 2, operands + 4);")
|
||||
|
||||
(define_insn "*swapdi_rex64"
|
||||
[(set (match_operand:DI 0 "register_operand" "+r")
|
||||
(match_operand:DI 1 "register_operand" "+r"))
|
||||
(set (match_dup 1)
|
||||
(match_dup 0))]
|
||||
"TARGET_64BIT"
|
||||
"xchg{q}\\t%1, %0"
|
||||
[(set_attr "type" "imov")
|
||||
(set_attr "pent_pair" "np")
|
||||
(set_attr "athlon_decode" "vector")
|
||||
(set_attr "mode" "DI")
|
||||
(set_attr "modrm" "0")
|
||||
(set_attr "ppro_uops" "few")])
|
||||
|
||||
|
||||
(define_expand "movsf"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "")
|
||||
@ -2197,7 +2566,7 @@
|
||||
(define_insn "*pushsf"
|
||||
[(set (match_operand:SF 0 "push_operand" "=<,<,<")
|
||||
(match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
|
||||
""
|
||||
"!TARGET_64BIT"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
@ -2224,6 +2593,37 @@
|
||||
[(set_attr "type" "multi,push,multi")
|
||||
(set_attr "mode" "SF,SI,SF")])
|
||||
|
||||
(define_insn "*pushsf_rex64"
|
||||
[(set (match_operand:SF 0 "push_operand" "=X,X,X")
|
||||
(match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
|
||||
"TARGET_64BIT"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0:
|
||||
/* %%% We loose REG_DEAD notes for controling pops if we split late. */
|
||||
operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
|
||||
operands[2] = stack_pointer_rtx;
|
||||
operands[3] = GEN_INT (8);
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
|
||||
case 1:
|
||||
return \"push{q}\\t%q1\";
|
||||
|
||||
case 2:
|
||||
return \"#\";
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "multi,push,multi")
|
||||
(set_attr "mode" "SF,DI,SF")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SF 0 "push_operand" "")
|
||||
(match_operand:SF 1 "memory_operand" ""))]
|
||||
@ -2240,10 +2640,17 @@
|
||||
(define_split
|
||||
[(set (match_operand:SF 0 "push_operand" "")
|
||||
(match_operand:SF 1 "register_operand" ""))]
|
||||
"ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
"!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
|
||||
(set (mem:SF (reg:SI 7)) (match_dup 1))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SF 0 "push_operand" "")
|
||||
(match_operand:SF 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
|
||||
(set (mem:SF (reg:DI 7)) (match_dup 1))])
|
||||
|
||||
(define_insn "*movsf_1"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
|
||||
(match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
|
||||
@ -2331,7 +2738,7 @@
|
||||
(define_insn "*pushdf_nointeger"
|
||||
[(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
|
||||
(match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
|
||||
"!TARGET_INTEGER_DFMODE_MOVES"
|
||||
"!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
@ -2361,7 +2768,7 @@
|
||||
(define_insn "*pushdf_integer"
|
||||
[(set (match_operand:DF 0 "push_operand" "=<,<,<")
|
||||
(match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
|
||||
"TARGET_INTEGER_DFMODE_MOVES"
|
||||
"TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
@ -2371,10 +2778,17 @@
|
||||
operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
|
||||
operands[2] = stack_pointer_rtx;
|
||||
operands[3] = GEN_INT (8);
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
if (TARGET_64BIT)
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
|
||||
|
||||
case 1:
|
||||
case 2:
|
||||
@ -2391,11 +2805,19 @@
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "push_operand" "")
|
||||
(match_operand:DF 1 "register_operand" ""))]
|
||||
"reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
"!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
|
||||
(set (mem:DF (reg:SI 7)) (match_dup 1))]
|
||||
"")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "push_operand" "")
|
||||
(match_operand:DF 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
|
||||
(set (mem:DF (reg:DI 7)) (match_dup 1))]
|
||||
"")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "push_operand" "")
|
||||
(match_operand:DF 1 "general_operand" ""))]
|
||||
@ -2673,10 +3095,16 @@
|
||||
operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
|
||||
operands[2] = stack_pointer_rtx;
|
||||
operands[3] = GEN_INT (16);
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
if (TARGET_64BIT)
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
|
||||
else
|
||||
return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
|
||||
|
||||
case 1:
|
||||
return \"#\";
|
||||
@ -2702,17 +3130,24 @@
|
||||
(define_split
|
||||
[(set (match_operand:XF 0 "push_operand" "")
|
||||
(match_operand:XF 1 "register_operand" ""))]
|
||||
"ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
"!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
|
||||
(set (mem:XF (reg:SI 7)) (match_dup 1))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:TF 0 "push_operand" "")
|
||||
(match_operand:TF 1 "register_operand" ""))]
|
||||
"ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
"!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
|
||||
(set (mem:TF (reg:SI 7)) (match_dup 1))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:TF 0 "push_operand" "")
|
||||
(match_operand:TF 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
|
||||
(set (mem:TF (reg:DI 7)) (match_dup 1))])
|
||||
|
||||
;; Do not use integer registers when optimizing for size
|
||||
(define_insn "*movxf_nointeger"
|
||||
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user