neon.md (vec_pack_trunc_<mode>): Instruction pattern for vmovn.
gcc/
2010-09-15 Tejas Belagod <tejas.belagod@arm.com>
* config/arm/neon.md (vec_pack_trunc_<mode>): Instruction
pattern for vmovn. Expansion in case of non
-mvectorize-with-neon-quad.
(neon_vec_pack_trunc_<mode>): Instruction pattern for vmovn for
non- -mvectorize-with-neon-quad case.
(move_lo_quad_<mode>): New expansion to vmov into low part.
(move_hi_quad_<mode>): New expansion to vmov into high part.
(move_lo_quad_v4si): Refactor to move_lo_quad_<mode> expansion.
(move_lo_quad_v4sf): Likewise.
(move_lo_quad_v8hi): Likewise.
(neon_move_lo_quad_<mode>): Instruction pattern for vmov into
low part.
(neon_move_hi_quad_<mode>): Instruction pattern for vmov into
high part.
* config/arm/iterators.md (ANY128): New mode iterator.
(V_narrow_pack): New mode attribute.
(V_HALF): Add attribute.
(V_DOUBLE): Add attribute.
(V_mode_nunits): Add attribute.
gcc/testsuite
2010-09-15 Tejas Belagod <tejas.belagod@arm.com>
* lib/target-supports.exp
(check_effective_target_vect_pack_trunc): Set vect_pack_trunc
supported flag to true for neon.
From-SVN: r164302
This commit is contained in:
Tejas Belagod
Tejas Belagod
parent
0064e82503
commit
0f38f22947
@ -1,3 +1,25 @@
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2010-09-15 Tejas Belagod <tejas.belagod@arm.com>
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* config/arm/neon.md (vec_pack_trunc_<mode>): Instruction
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pattern for vmovn. Expansion in case of non
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-mvectorize-with-neon-quad.
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(neon_vec_pack_trunc_<mode>): Instruction pattern for vmovn for
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non- -mvectorize-with-neon-quad case.
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(move_lo_quad_<mode>): New expansion to vmov into low part.
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(move_hi_quad_<mode>): New expansion to vmov into high part.
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(move_lo_quad_v4si): Refactor to move_lo_quad_<mode> expansion.
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(move_lo_quad_v4sf): Likewise.
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(move_lo_quad_v8hi): Likewise.
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(neon_move_lo_quad_<mode>): Instruction pattern for vmov into
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low part.
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(neon_move_hi_quad_<mode>): Instruction pattern for vmov into
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high part.
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* config/arm/iterators.md (ANY128): New mode iterator.
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(V_narrow_pack): New mode attribute.
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(V_HALF): Add attribute.
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(V_DOUBLE): Add attribute.
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(V_mode_nunits): Add attribute.
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2010-09-15 Eric Botcazou <ebotcazou@adacore.com>
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* config/alpha/alpha.c (alpha_expand_prologue): If stack checking
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@ -28,6 +28,8 @@
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;; registers.
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(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
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(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
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;; A list of integer modes that are up to one word long
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(define_mode_iterator QHSI [QI HI SI])
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@ -227,9 +229,13 @@
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;; Narrower modes with the same number of elements.
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(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
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;; Narrower modes with double the number of elements.
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(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
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(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
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;; Modes with half the number of equal-sized elements.
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(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
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(V4SI "V2SI") (V4SF "V2SF")
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(V4SI "V2SI") (V4SF "V2SF") (V2DF "DF")
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(V2DI "DI")])
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;; Same, but lower-case.
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@ -239,7 +245,7 @@
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;; Modes with twice the number of equal-sized elements.
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(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
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(V2SI "V4SI") (V2SF "V4SF")
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(V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
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(DI "V2DI")])
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;; Same, but lower-case.
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@ -362,7 +368,8 @@
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(V4HI "4") (V8HI "8")
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(V2SI "2") (V4SI "4")
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(V2SF "2") (V4SF "4")
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(DI "1") (V2DI "2")])
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(DI "1") (V2DI "2")
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(DF "1") (V2DF "2")])
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;; Same as V_widen, but lower-case.
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(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
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@ -1117,12 +1117,13 @@
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; vector registers. Make an attempt at removing unnecessary moves, though
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; we're really at the mercy of the register allocator.
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(define_insn "move_lo_quad_v4si"
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[(set (match_operand:V4SI 0 "s_register_operand" "+w")
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(vec_concat:V4SI
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(match_operand:V2SI 1 "s_register_operand" "w")
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(vec_select:V2SI (match_dup 0)
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(parallel [(const_int 2) (const_int 3)]))))]
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(define_insn "neon_move_lo_quad_<mode>"
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[(set (match_operand:ANY128 0 "s_register_operand" "+w")
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(vec_concat:ANY128
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(match_operand:<V_HALF> 1 "s_register_operand" "w")
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(vec_select:<V_HALF>
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(match_dup 0)
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(match_operand:ANY128 2 "vect_par_constant_high" ""))))]
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"TARGET_NEON"
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{
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int dest = REGNO (operands[0]);
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@ -1136,66 +1137,61 @@
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "move_lo_quad_v4sf"
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[(set (match_operand:V4SF 0 "s_register_operand" "+w")
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(vec_concat:V4SF
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(match_operand:V2SF 1 "s_register_operand" "w")
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(vec_select:V2SF (match_dup 0)
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(parallel [(const_int 2) (const_int 3)]))))]
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(define_insn "neon_move_hi_quad_<mode>"
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[(set (match_operand:ANY128 0 "s_register_operand" "+w")
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(vec_concat:ANY128
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(match_operand:<V_HALF> 1 "s_register_operand" "w")
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(vec_select:<V_HALF>
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(match_dup 0)
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(match_operand:ANY128 2 "vect_par_constant_low" ""))))]
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"TARGET_NEON"
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{
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int dest = REGNO (operands[0]);
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int src = REGNO (operands[1]);
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if (dest != src)
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return "vmov\t%e0, %P1";
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return "vmov\t%f0, %P1";
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else
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return "";
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}
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "move_lo_quad_v8hi"
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[(set (match_operand:V8HI 0 "s_register_operand" "+w")
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(vec_concat:V8HI
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(match_operand:V4HI 1 "s_register_operand" "w")
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(vec_select:V4HI (match_dup 0)
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(parallel [(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)]))))]
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"TARGET_NEON"
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(define_expand "move_hi_quad_<mode>"
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[(match_operand:ANY128 0 "s_register_operand" "")
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(match_operand:<V_HALF> 1 "s_register_operand" "")]
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"TARGET_NEON"
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{
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int dest = REGNO (operands[0]);
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int src = REGNO (operands[1]);
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rtvec v = rtvec_alloc (<V_mode_nunits>/2);
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rtx t1;
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int i;
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if (dest != src)
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return "vmov\t%e0, %P1";
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else
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return "";
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}
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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for (i=0; i < (<V_mode_nunits>/2); i++)
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RTVEC_ELT (v, i) = GEN_INT (i);
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(define_insn "move_lo_quad_v16qi"
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[(set (match_operand:V16QI 0 "s_register_operand" "+w")
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(vec_concat:V16QI
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(match_operand:V8QI 1 "s_register_operand" "w")
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(vec_select:V8QI (match_dup 0)
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(parallel [(const_int 8) (const_int 9)
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(const_int 10) (const_int 11)
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(const_int 12) (const_int 13)
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(const_int 14) (const_int 15)]))))]
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"TARGET_NEON"
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_move_hi_quad_<mode> (operands[0], operands[1], t1));
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DONE;
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})
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(define_expand "move_lo_quad_<mode>"
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[(match_operand:ANY128 0 "s_register_operand" "")
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(match_operand:<V_HALF> 1 "s_register_operand" "")]
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"TARGET_NEON"
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{
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int dest = REGNO (operands[0]);
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int src = REGNO (operands[1]);
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rtvec v = rtvec_alloc (<V_mode_nunits>/2);
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rtx t1;
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int i;
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if (dest != src)
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return "vmov\t%e0, %P1";
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else
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return "";
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}
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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for (i=0; i < (<V_mode_nunits>/2); i++)
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RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_move_lo_quad_<mode> (operands[0], operands[1], t1));
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DONE;
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})
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;; Reduction operations
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@ -5390,3 +5386,38 @@
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}
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)
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(define_insn "vec_pack_trunc_<mode>"
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[(set (match_operand:<V_narrow_pack> 0 "register_operand" "=&w")
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(vec_concat:<V_narrow_pack>
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(truncate:<V_narrow>
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(match_operand:VN 1 "register_operand" "w"))
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(truncate:<V_narrow>
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(match_operand:VN 2 "register_operand" "w"))))]
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"TARGET_NEON"
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"vmovn.i<V_sz_elem>\t%e0, %q1\n\tvmovn.i<V_sz_elem>\t%f0, %q2"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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;; For the non-quad case.
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(define_insn "neon_vec_pack_trunc_<mode>"
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[(set (match_operand:<V_narrow> 0 "register_operand" "=w")
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(truncate:<V_narrow> (match_operand:VN 1 "register_operand" "")))]
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"TARGET_NEON"
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"vmovn.i<V_sz_elem>\t%0, %q1"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_pack_trunc_<mode>"
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[(match_operand:<V_narrow_pack> 0 "register_operand" "")
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(match_operand:VSHFT 1 "register_operand" "")
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(match_operand:VSHFT 2 "register_operand")]
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"TARGET_NEON"
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{
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rtx tempreg = gen_reg_rtx (<V_DOUBLE>mode);
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emit_insn (gen_move_lo_quad_<V_double> (tempreg, operands[1]));
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emit_insn (gen_move_hi_quad_<V_double> (tempreg, operands[2]));
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emit_insn (gen_neon_vec_pack_trunc_<V_double> (operands[0], tempreg));
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DONE;
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})
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@ -1,3 +1,9 @@
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2010-09-15 Tejas Belagod <tejas.belagod@arm.com>
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* lib/target-supports.exp
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(check_effective_target_vect_pack_trunc): Set vect_pack_trunc
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supported flag to true for neon.
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2010-09-15 Paolo Carlini <paolo.carlini@oracle.com>
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PR c++/45665
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@ -2676,7 +2676,8 @@ proc check_effective_target_vect_pack_trunc { } {
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if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
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|| [istarget i?86-*-*]
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|| [istarget x86_64-*-*]
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|| [istarget spu-*-*] } {
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|| [istarget spu-*-*]
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|| ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
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set et_vect_pack_trunc_saved 1
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}
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}
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