h8300.c (print_operand): Modify case 'V' and case 'W' print operands for HI mode.
* config/h8300/h8300.c (print_operand) : Modify case 'V' and case 'W' print operands for HI mode. * config/h8300/h8300.h (Y0, Y2) : New constraints. * config/h8300/h8300.md (bclrqi_msx, bclrhi_msx): New patterns (bsetqi_msx, bsethi_msx, bnotqi_msx, bnothi_msx): Likewise. * config/h8300/predicate.md (bit_register_indirect_operand): New. From-SVN: r158452
This commit is contained in:
Kaushik Phatak
Jeff Law
parent
fcd3c5a9be
commit
0f6b820c5d
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@ -41,6 +41,13 @@
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2010-04-12 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* config/h8300/h8300.c (print_operand) : Modify case 'V' and
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case 'W' print operands for HI mode.
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* config/h8300/h8300.h (Y0, Y2) : New constraints.
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* config/h8300/h8300.md (bclrqi_msx, bclrhi_msx): New patterns
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(bsetqi_msx, bsethi_msx, bnotqi_msx, bnothi_msx): Likewise.
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* config/h8300/predicate.md (bit_register_indirect_operand): New.
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* config/h8300/h8300.h (OK_FOR_U): Support 'U' constraint for H8300SX.
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* config/h8300/h8300.md (movqi_h8sx, movhi_h8sx, movsi_h8sx,
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@ -1468,12 +1468,20 @@ print_operand (FILE *file, rtx x, int code)
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goto def;
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break;
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case 'V':
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bitint = exact_log2 (INTVAL (x) & 0xff);
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bitint = (INTVAL (x) & 0xffff);
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if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
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bitint = exact_log2 (bitint & 0xff);
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else
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bitint = exact_log2 ((bitint >> 8) & 0xff);
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gcc_assert (bitint >= 0);
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fprintf (file, "#%d", bitint);
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break;
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case 'W':
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bitint = exact_log2 ((~INTVAL (x)) & 0xff);
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bitint = ((~INTVAL (x)) & 0xffff);
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if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
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bitint = exact_log2 (bitint & 0xff);
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else
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bitint = (exact_log2 ((bitint >> 8) & 0xff));
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gcc_assert (bitint >= 0);
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fprintf (file, "#%d", bitint);
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break;
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@ -819,15 +819,25 @@ struct cum_arg
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((STR)[1] == 'U' ? 2 \
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: 0)
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/* We don't have any constraint starting with Y yet, but before
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someone uses it for a one-letter constraint and we're left without
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any upper-case constraints left, we reserve it for extensions
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here. */
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#define OK_FOR_Y(OP, STR) \
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(0)
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/* Multi-letter constraints starting with Y are to be used for operands
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that are constant immediates and have single 1 or 0 in their binary
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representation. */
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#define OK_FOR_Y2(OP) \
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((GET_CODE (OP) == CONST_INT) && (exact_log2 (INTVAL (OP) & 0xff) != -1))
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#define OK_FOR_Y0(OP) \
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((GET_CODE (OP) == CONST_INT) && (exact_log2 (~INTVAL (OP) & 0xff) != -1))
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#define OK_FOR_Y(OP, STR) \
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((STR)[1] == '2' ? OK_FOR_Y2 (OP) \
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: (STR)[1] == '0' ? OK_FOR_Y0 (OP) \
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: 0)
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#define CONSTRAINT_LEN_FOR_Y(STR) \
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(0)
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((STR)[1] == '2' ? 2 \
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: (STR)[1] == '0' ? 2 \
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: 0)
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#define OK_FOR_Z(OP) \
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(TARGET_H8300SX \
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@ -1762,7 +1762,34 @@
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;; ----------------------------------------------------------------------
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;; AND INSTRUCTIONS
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;; ----------------------------------------------------------------------
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(define_insn "bclrqi_msx"
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[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
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(and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
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(match_operand:QI 2 "single_zero_operand" "Y0")))]
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"TARGET_H8300SX"
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"bclr\\t%W2,%0"
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[(set_attr "length" "8")])
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(define_split
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
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(and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_zero_operand" "Y0")))]
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"TARGET_H8300SX"
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[(set (match_dup 0)
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(and:QI (match_dup 1)
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(match_dup 2)))]
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{
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operands[0] = adjust_address (operands[0], QImode, 1);
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operands[1] = adjust_address (operands[1], QImode, 1);
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})
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(define_insn "bclrhi_msx"
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
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(and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_zero_operand" "Y0")))]
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"TARGET_H8300SX"
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"bclr\\t%W2,%0"
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[(set_attr "length" "8")])
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(define_insn "*andqi3_2"
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[(set (match_operand:QI 0 "bit_operand" "=rQ,r")
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(and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
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@ -1866,6 +1893,34 @@
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;; ----------------------------------------------------------------------
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;; OR INSTRUCTIONS
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;; ----------------------------------------------------------------------
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(define_insn "bsetqi_msx"
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[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
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(ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
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(match_operand:QI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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"bset\\t%V2,%0"
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[(set_attr "length" "8")])
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(define_split
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
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(ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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[(set (match_dup 0)
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(ior:QI (match_dup 1)
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(match_dup 2)))]
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{
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operands[0] = adjust_address (operands[0], QImode, 1);
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operands[1] = adjust_address (operands[1], QImode, 1);
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})
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(define_insn "bsethi_msx"
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
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(ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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"bset\\t%V2,%0"
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[(set_attr "length" "8")])
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(define_insn "iorqi3_1"
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[(set (match_operand:QI 0 "bit_operand" "=rQ,U")
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@ -1904,6 +1959,34 @@
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;; ----------------------------------------------------------------------
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;; XOR INSTRUCTIONS
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;; ----------------------------------------------------------------------
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(define_insn "bnotqi_msx"
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[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
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(xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
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(match_operand:QI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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"bnot\\t%V2,%0"
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[(set_attr "length" "8")])
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(define_split
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
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(xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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[(set (match_dup 0)
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(xor:QI (match_dup 1)
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(match_dup 2)))]
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{
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operands[0] = adjust_address (operands[0], QImode, 1);
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operands[1] = adjust_address (operands[1], QImode, 1);
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})
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(define_insn "bnothi_msx"
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
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(xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_one_operand" "Y2")))]
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"TARGET_H8300SX"
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"bnot\\t%V2,%0"
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[(set_attr "length" "8")])
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(define_insn "xorqi3_1"
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[(set (match_operand:QI 0 "bit_operand" "=r,U")
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@ -356,6 +356,17 @@
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&& OK_FOR_U (op));
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})
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;; Return nonzero if OP is indirect register or constant memory
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;; suitable for bit manipulation insns.
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(define_predicate "bit_register_indirect_operand"
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(match_code "mem")
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{
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return (GET_CODE (op) == MEM
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&& (GET_CODE (XEXP (op, 0)) == REG
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|| GET_CODE (XEXP (op, 0)) == CONST_INT));
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})
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;; Return nonzero if X is a stack pointer.
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(define_predicate "stack_pointer_operand"
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