[PATCH][AARCH64]Add csneg3_uxtw_insn pattern
gcc/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern. gcc/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gcc.target/aarch64/csneg-1.c: Update test. From-SVN: r228387
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@ -3,6 +3,10 @@
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* config/sh/sh.md: Add new unnamed split pattern to handle movt-movt
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sequences.
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2015-10-02 Renlin Li <renlin.li@arm.com>
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* config/aarch64/aarch64.md (csneg3_insn_uxtw): New pattern.
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2015-10-02 Renlin Li <renlin.li@arm.com>
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PR target/66776
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@ -3144,6 +3144,18 @@
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[(set_attr "type" "csel")]
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)
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(define_insn "csneg3_uxtw_insn"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(if_then_else:SI
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(match_operand 1 "aarch64_comparison_operation" "")
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(neg:SI (match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "aarch64_reg_or_zero" "rZ"))))]
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""
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"csneg\\t%w0, %w3, %w2, %M1"
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[(set_attr "type" "csel")]
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)
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(define_insn "csneg3<mode>_insn"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(if_then_else:GPI
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@ -1,3 +1,7 @@
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2015-10-02 Renlin Li <renlin.li@arm.com>
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* gcc.target/aarch64/csneg-1.c: Update.
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2015-10-02 Renlin Li <renlin.li@arm.com>
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PR target/66776
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@ -56,3 +56,15 @@ int test_csneg_cmp(int x)
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x = -x;
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return x;
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}
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unsigned long long
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test_csneg_uxtw (unsigned int a,
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unsigned int b,
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unsigned int c)
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{
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/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
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/* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */
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unsigned int val;
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val = a ? b: -c;
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return val;
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}
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