PR target/77822: S390: Validate argument range of {zero,sign}_extract.
With some undefined code, combine generates patterns where the arguments to
*_extract are out of range, e.b. a negative bit position. If the s390 backend
accepts these, they lead to not just undefined behaviour but invalid assembly
instructions (argument out of the allowed range). So this patch makes sure
that the rtl expressions with out of range arguments are rejected.
gcc/ChangeLog:
2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com>
PR target/77822
* config/s390/s390.md ("extzv")
("*extzv<mode><clobbercc_or_nocc>")
("*extzvdi<clobbercc_or_nocc>_lshiftrt")
("*<risbg_n>_ior_and_sr_ze")
("*extract1bitdi<clobbercc_or_nocc>")
("*insv<mode><clobbercc_or_nocc>", "*insv_rnsbg_noshift")
("*insv_rnsbg_srl", "*insv<mode>_mem_reg")
("*insvdi_mem_reghigh", "*insvdi_reg_imm"): Use EXTRACT_ARGS_IN_RANGE
to validate the arguments of zero_extract and sign_extract.
gcc/testsuite/ChangeLog:
2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com>
PR target/77822
* gcc.target/s390/s390.exp: Support .C tests.
* gcc.target/s390/pr77822-2.c: New test.
* gcc.target/s390/pr77822-1.C: New test.
From-SVN: r243160
This commit is contained in:
Dominik Vogt
Andreas Krebbel
parent
8f61415f1f
commit
0f6f72e805
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@ -1,3 +1,16 @@
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2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com>
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PR target/77822
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* config/s390/s390.md ("extzv")
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("*extzv<mode><clobbercc_or_nocc>")
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("*extzvdi<clobbercc_or_nocc>_lshiftrt")
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("*<risbg_n>_ior_and_sr_ze")
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("*extract1bitdi<clobbercc_or_nocc>")
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("*insv<mode><clobbercc_or_nocc>", "*insv_rnsbg_noshift")
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("*insv_rnsbg_srl", "*insv<mode>_mem_reg")
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("*insvdi_mem_reghigh", "*insvdi_reg_imm"): Use EXTRACT_ARGS_IN_RANGE
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to validate the arguments of zero_extract and sign_extract.
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2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com>
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PR target/77822
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@ -3741,6 +3741,8 @@
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(clobber (reg:CC CC_REGNUM))])]
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"TARGET_Z10"
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{
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if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
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FAIL;
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/* Starting with zEC12 there is risbgn not clobbering CC. */
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if (TARGET_ZEC12)
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{
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@ -3760,7 +3762,9 @@
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(match_operand 2 "const_int_operand" "") ; size
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(match_operand 3 "const_int_operand" ""))) ; start
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]
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"<z10_or_zEC12_cond>"
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"<z10_or_zEC12_cond>
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
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GET_MODE_BITSIZE (<MODE>mode))"
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"<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
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[(set_attr "op_type" "RIE")
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(set_attr "z10prop" "z10_super_E1")])
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@ -3773,6 +3777,7 @@
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(lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
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(match_operand:DI 4 "nonzero_shift_count_operand" "")))]
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"<z10_or_zEC12_cond>
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
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&& 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
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"<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
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[(set_attr "op_type" "RIE")
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@ -3791,6 +3796,7 @@
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(match_operand 5 "const_int_operand" "")) ; start
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4)))]
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"<z10_or_zEC12_cond>
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
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&& UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
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"<risbg_n>\t%0,%3,64-%4,63,%4+%5"
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[(set_attr "op_type" "RIE")
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@ -3804,7 +3810,8 @@
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(const_int 1) ; size
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(match_operand 2 "const_int_operand" "")) ; start
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(const_int 0)))]
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"<z10_or_zEC12_cond>"
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"<z10_or_zEC12_cond>
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&& EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
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"<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
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[(set_attr "op_type" "RIE")
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(set_attr "z10prop" "z10_super_E1")])
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@ -3919,6 +3926,8 @@
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(match_operand 2 "const_int_operand" "I")) ; pos
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(match_operand:GPR 3 "nonimmediate_operand" "d"))]
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"<z10_or_zEC12_cond>
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
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GET_MODE_BITSIZE (<MODE>mode))
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&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
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"<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
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[(set_attr "op_type" "RIE")
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@ -4214,6 +4223,7 @@
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(match_operand:DI 3 "nonimmediate_operand" "d")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
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&& INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
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"rnsbg\t%0,%3,%2,63,0"
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[(set_attr "op_type" "RIE")])
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@ -4230,6 +4240,7 @@
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(match_operand:DI 4 "nonimmediate_operand" "d")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
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&& INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
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"rnsbg\t%0,%4,%2,%2+%1-1,%3"
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[(set_attr "op_type" "RIE")])
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@ -4239,7 +4250,8 @@
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(match_operand 1 "const_int_operand" "n,n")
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(const_int 0))
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(match_operand:W 2 "register_operand" "d,d"))]
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"INTVAL (operands[1]) > 0
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"EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
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&& INTVAL (operands[1]) > 0
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&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
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&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
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{
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@ -4260,6 +4272,7 @@
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(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
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(const_int 32)))]
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"TARGET_ZARCH
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&& EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
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&& INTVAL (operands[1]) > 0
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&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
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&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
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@ -4278,6 +4291,7 @@
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(match_operand 1 "const_int_operand" "n"))
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(match_operand:DI 2 "const_int_operand" "n"))]
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"TARGET_ZARCH
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&& EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
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&& INTVAL (operands[1]) >= 0
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&& INTVAL (operands[1]) < BITS_PER_WORD
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&& INTVAL (operands[1]) % 16 == 0"
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@ -1,3 +1,10 @@
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2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com>
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PR target/77822
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* gcc.target/s390/s390.exp: Support .C tests.
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* gcc.target/s390/pr77822-2.c: New test.
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* gcc.target/s390/pr77822-1.C: New test.
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2016-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* gcc.target/s390/vector/vec-nopeel-1.c: New test.
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@ -0,0 +1,21 @@
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/* Regression test for PR/77822. */
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=zEC12" } */
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class A {
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void m_fn1();
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char m_datawidth;
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char m_subunits;
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int m_subunit_infos[];
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};
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int a;
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long b;
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void A::m_fn1() {
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int c = 32, d = m_datawidth / c;
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for (int e = 0; e < d; e++) {
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int f = e * 32;
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if (b >> f & 1)
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m_subunit_infos[m_subunits] = a;
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}
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}
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@ -0,0 +1,307 @@
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/* This testcase checks that the shift operand of r*sbg instructions is in
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range. */
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=zEC12 -Wno-shift-count-overflow" } */
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int g;
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void pos_ll_129 (long long b)
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{
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if (b >> 129 & 1)
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g = b;
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}
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void sizepos_ll_134 (long long b)
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{
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if (b >> 134 & 1)
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g = b;
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}
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void pos_ll_65 (long long b)
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{
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if (b >> 65 & 1)
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g = b;
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}
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void sizepos_ll_70 (long long b)
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{
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if (b >> 70 & 1)
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g = b;
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}
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void pos_ll_33 (long long b)
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{
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if (b >> 33 & 1)
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g = b;
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}
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void sizepos_ll_38 (long long b)
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{
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if (b >> 38 & 1)
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g = b;
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}
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void pos_ll_17 (long long b)
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{
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if (b >> 17 & 1)
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g = b;
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}
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void sizepos_ll_22 (long long b)
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{
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if (b >> 22 & 1)
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g = b;
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}
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void pos_ll_8 (long long b)
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{
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if (b >> 8 & 1)
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g = b;
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}
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void sizepos_ll_13 (long long b)
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{
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if (b >> 13 & 1)
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g = b;
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}
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void pos_l_129 (long b)
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{
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if (b >> 129 & 1)
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g = b;
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}
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void sizepos_l_134 (long b)
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{
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if (b >> 134 & 1)
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g = b;
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}
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void pos_l_65 (long b)
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{
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if (b >> 65 & 1)
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g = b;
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}
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void sizepos_l_70 (long b)
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{
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if (b >> 70 & 1)
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g = b;
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}
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void pos_l_33 (long b)
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{
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if (b >> 33 & 1)
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g = b;
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}
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void sizepos_l_38 (long b)
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{
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if (b >> 38 & 1)
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g = b;
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}
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void pos_l_17 (long b)
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{
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if (b >> 17 & 1)
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g = b;
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}
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void sizepos_l_22 (long b)
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{
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if (b >> 22 & 1)
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g = b;
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}
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void pos_l_8 (long b)
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{
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if (b >> 8 & 1)
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g = b;
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}
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void sizepos_l_13 (long b)
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{
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if (b >> 13 & 1)
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g = b;
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}
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void pos_i_129 (int b)
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{
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if (b >> 129 & 1)
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g = b;
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}
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void sizepos_i_134 (int b)
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{
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if (b >> 134 & 1)
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g = b;
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}
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void pos_i_65 (int b)
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{
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if (b >> 65 & 1)
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g = b;
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}
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void sizepos_i_70 (int b)
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{
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if (b >> 70 & 1)
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g = b;
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}
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void pos_i_33 (int b)
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{
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if (b >> 33 & 1)
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g = b;
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}
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void sizepos_i_38 (int b)
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{
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if (b >> 38 & 1)
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g = b;
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}
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void pos_i_17 (int b)
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{
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if (b >> 17 & 1)
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g = b;
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}
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void sizepos_i_22 (int b)
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{
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if (b >> 22 & 1)
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g = b;
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}
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void pos_i_8 (int b)
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{
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if (b >> 8 & 1)
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g = b;
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}
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void sizepos_i_13 (int b)
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{
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if (b >> 13 & 1)
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g = b;
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}
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void pos_s_129 (short b)
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{
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if (b >> 129 & 1)
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g = b;
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}
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void sizepos_s_134 (short b)
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{
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if (b >> 134 & 1)
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g = b;
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}
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void pos_s_65 (short b)
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{
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if (b >> 65 & 1)
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g = b;
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}
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void sizepos_s_70 (short b)
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{
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if (b >> 70 & 1)
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g = b;
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}
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void pos_s_33 (short b)
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{
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if (b >> 33 & 1)
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g = b;
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}
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void sizepos_s_38 (short b)
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{
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if (b >> 38 & 1)
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g = b;
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}
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void pos_s_17 (short b)
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{
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if (b >> 17 & 1)
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g = b;
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}
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void sizepos_s_22 (short b)
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{
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if (b >> 22 & 1)
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g = b;
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}
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void pos_s_8 (short b)
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{
|
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if (b >> 8 & 1)
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g = b;
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}
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|
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void sizepos_s_13 (short b)
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{
|
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if (b >> 13 & 1)
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g = b;
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}
|
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|
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void pos_c_129 (signed char b)
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{
|
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if (b >> 129 & 1)
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g = b;
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}
|
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|
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void sizepos_c_134 (signed char b)
|
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{
|
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if (b >> 134 & 1)
|
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g = b;
|
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}
|
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|
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void pos_c_65 (signed char b)
|
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{
|
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if (b >> 65 & 1)
|
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g = b;
|
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}
|
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|
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void sizepos_c_70 (signed char b)
|
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{
|
||||
if (b >> 70 & 1)
|
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g = b;
|
||||
}
|
||||
|
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void pos_c_33 (signed char b)
|
||||
{
|
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if (b >> 33 & 1)
|
||||
g = b;
|
||||
}
|
||||
|
||||
void sizepos_c_38 (signed char b)
|
||||
{
|
||||
if (b >> 38 & 1)
|
||||
g = b;
|
||||
}
|
||||
|
||||
void pos_c_17 (signed char b)
|
||||
{
|
||||
if (b >> 17 & 1)
|
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g = b;
|
||||
}
|
||||
|
||||
void sizepos_c_22 (signed char b)
|
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{
|
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if (b >> 22 & 1)
|
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g = b;
|
||||
}
|
||||
|
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void pos_c_8 (signed char b)
|
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{
|
||||
if (b >> 8 & 1)
|
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g = b;
|
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}
|
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|
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void sizepos_c_13 (signed char b)
|
||||
{
|
||||
if (b >> 13 & 1)
|
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g = b;
|
||||
}
|
||||
|
|
@ -90,16 +90,16 @@ dg-init
|
|||
set md_tests $srcdir/$subdir/md/*.c
|
||||
|
||||
# Main loop.
|
||||
dg-runtest [lsort [prune [glob -nocomplain $srcdir/$subdir/*.\[cS\]] \
|
||||
dg-runtest [lsort [prune [glob -nocomplain $srcdir/$subdir/*.{c,S,C}] \
|
||||
$md_tests]] "" $DEFAULT_CFLAGS
|
||||
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*vector*/*.\[cS\]]] \
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*vector*/*.]] \
|
||||
"" $DEFAULT_CFLAGS
|
||||
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/target-attribute/*.\[cS\]]] \
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/target-attribute/*.{c,S,C}]] \
|
||||
"" $DEFAULT_CFLAGS
|
||||
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/md/*.\[cS\]]] \
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/md/*.{c,S,C}]] \
|
||||
"" $DEFAULT_CFLAGS
|
||||
|
||||
# Additional hotpatch torture tests.
|
||||
|
|
|
|||
Loading…
Reference in New Issue