AVX512: Fix embedded rounding/SAE specifier position.
gcc/ PR target/67895 * config/i386/sse.md (define_insn "sse_cvtsi2ss<round_name>"): Adjust embedded rounding/SAE specifier position. (define_insn "sse_cvtsi2ssq<round_name>"): Likewise. (define_insn "cvtusi2<ssescalarmodesuffix>32<round_name>"): Likewise. (define_insn "cvtusi2<ssescalarmodesuffix>64<round_name>"): Likewise. (define_insn "sse2_cvtsi2sdq<round_name>"): Likewise. (define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"): Likewise. (define_insn "avx512dq_ranges<mode><round_saeonly_name>"): Likewise. gcc/testsuite PR target/67895 * gcc.target/i386/avx512dq-vrangepd-1.c: Adjust assembly regexp. * gcc.target/i386/avx512dq-vrangeps-1.c: Likewise. * gcc.target/i386/avx512dq-vrangesd-1.c: Likewise. * gcc.target/i386/avx512dq-vrangess-1.c: Likewise. * gcc.target/i386/avx512f-vcvtsi2sd64-1.c: Likewise. * gcc.target/i386/avx512f-vcvtsi2ss-1.c: Likewise. * gcc.target/i386/avx512f-vcvtsi2ss64-1.c: Likewise. * gcc.target/i386/avx512f-vcvtusi2sd64-1.c: Likewise. * gcc.target/i386/avx512f-vcvtusi2ss-1.c: Likewise. * gcc.target/i386/avx512f-vcvtusi2ss64-1.c: Likewise. From-SVN: r228660
This commit is contained in:
Alexander Fomin
Alexander Fomin
parent
9e531d3749
commit
0fc87f2fc2
@ -1,3 +1,16 @@
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2015-10-09 Alexander Fomin <alexander.fomin@intel.com>
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PR target/67895
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* config/i386/sse.md (define_insn "sse_cvtsi2ss<round_name>"):
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Adjust embedded rounding/SAE specifier position.
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(define_insn "sse_cvtsi2ssq<round_name>"): Likewise.
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(define_insn "cvtusi2<ssescalarmodesuffix>32<round_name>"): Likewise.
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(define_insn "cvtusi2<ssescalarmodesuffix>64<round_name>"): Likewise.
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(define_insn "sse2_cvtsi2sdq<round_name>"): Likewise.
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(define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"):
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Likewise.
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(define_insn "avx512dq_ranges<mode><round_saeonly_name>"): Likewise.
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2015-10-09 Martin Jambor <mjambor@suse.cz>
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tree-optimization/67794
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@ -4014,7 +4014,7 @@
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"@
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cvtsi2ss\t{%2, %0|%0, %2}
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cvtsi2ss\t{%2, %0|%0, %2}
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vcvtsi2ss\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}"
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vcvtsi2ss\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "vector,double,*")
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@ -4036,7 +4036,7 @@
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"@
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cvtsi2ssq\t{%2, %0|%0, %2}
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cvtsi2ssq\t{%2, %0|%0, %2}
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vcvtsi2ssq\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}"
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vcvtsi2ssq\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "vector,double,*")
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@ -4149,7 +4149,7 @@
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(match_operand:VF_128 1 "register_operand" "v")
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(const_int 1)))]
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"TARGET_AVX512F && <round_modev4sf_condition>"
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"vcvtusi2<ssescalarmodesuffix>\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}"
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"vcvtusi2<ssescalarmodesuffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -4163,7 +4163,7 @@
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(match_operand:VF_128 1 "register_operand" "v")
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(const_int 1)))]
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"TARGET_AVX512F && TARGET_64BIT"
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"vcvtusi2<ssescalarmodesuffix>\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}"
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"vcvtusi2<ssescalarmodesuffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
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[(set_attr "type" "sseicvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -4429,7 +4429,7 @@
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"@
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cvtsi2sdq\t{%2, %0|%0, %2}
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cvtsi2sdq\t{%2, %0|%0, %2}
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vcvtsi2sdq\t{<round_op3>%2, %1, %0|%0, %1, %2<round_op3>}"
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vcvtsi2sdq\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "double,direct,*")
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@ -18684,7 +18684,7 @@
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(match_operand:SI 3 "const_0_to_15_operand")]
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UNSPEC_RANGE))]
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"TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
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"vrange<ssemodesuffix>\t{<round_saeonly_mask_op4>%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3<round_saeonly_mask_op4>}"
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"vrange<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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@ -18700,7 +18700,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_AVX512DQ"
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"vrange<ssescalarmodesuffix>\t{<round_saeonly_op4>%3, %2, %1, %0|%0, %1, %2, %3<round_saeonly_op4>}"
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"vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1, %2<round_saeonly_op4>, %3}"
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<MODE>")])
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@ -1,3 +1,17 @@
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2015-10-09 Alexander Fomin <alexander.fomin@intel.com>
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PR target/67895
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* gcc.target/i386/avx512dq-vrangepd-1.c: Adjust assembly regexp.
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* gcc.target/i386/avx512dq-vrangeps-1.c: Likewise.
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* gcc.target/i386/avx512dq-vrangesd-1.c: Likewise.
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* gcc.target/i386/avx512dq-vrangess-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtsi2sd64-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtsi2ss-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtsi2ss64-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtusi2sd64-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtusi2ss-1.c: Likewise.
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* gcc.target/i386/avx512f-vcvtusi2ss64-1.c: Likewise.
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2015-10-09 David Malcolm <dmalcolm@redhat.com>
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* lib/multiline.exp: New file.
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@ -1,15 +1,15 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512dq -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangepd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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@ -3,15 +3,15 @@
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangeps\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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@ -1,7 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512dq -O2" } */
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/* { dg-final { scan-assembler-times "vrangesd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangesd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangesd\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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@ -1,7 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512dq -O2" } */
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/* { dg-final { scan-assembler-times "vrangess\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangess\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vrangess\[ \\t\]+\[^\$\n\]*\\$\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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@ -1,6 +1,6 @@
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/* { dg-do compile { target { ! { ia32 } } } } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtsi2sdq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtsi2sdq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtsi2ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtsi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* { dg-do compile { target { ! { ia32 } } } } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtsi2ssq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtsi2ssq\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* { dg-do compile { target { ! { ia32 } } } } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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/* { dg-do compile { target { ! { ia32 } } } } */
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/* { dg-options "-mavx512f -O2" } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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