[AArch64] Rework SVE INC/DEC handling
The scalar addition patterns allowed all the VL constants that
ADDVL and ADDPL allow, but wrote the instructions as INC or DEC
if possible (i.e. adding or subtracting a number of elements * [1, 16]
when the source and target registers the same). That works for the
cases that the autovectoriser needs, but there are a few constants
that INC and DEC can handle but ADDPL and ADDVL can't. E.g.:
inch x0, all, mul #9
is not a multiple of the number of bytes in an SVE register, and so
can't use ADDVL. It represents 36 times the number of bytes in an
SVE predicate, putting it outside the range of ADDPL.
This patch therefore adds separate alternatives for INC and DEC,
tied to a new Uai constraint. It also adds an explicit "scalar"
or "vector" to the function names, to avoid a clash with the
existing support for vector INC and DEC.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
(aarch64_output_sve_scalar_inc_dec): Declare.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.
* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
(aarch64_output_sve_scalar_inc_dec): New functions.
(aarch64_output_sve_addvl_addpl): Remove the base and offset
arguments. Only handle true ADDVL and ADDPL instructions;
don't emit an INC or DEC.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
(aarch64_sve_plus_immediate): New predicates.
(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
rather than aarch64_sve_addvl_addpl_immediate.
(aarch64_sve_inc_dec_immediate): Rename to...
(aarch64_sve_vector_inc_dec_immediate): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
(aarch64_sve_add_operand): Update accordingly.
* config/aarch64/constraints.md (Uai): New constraint.
(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
operand into a register if it satisfies aarch64_sve_plus_immediate.
(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
for Uai. Update calls to aarch64_output_sve_addvl_addpl.
* config/aarch64/aarch64-sve.md (add<mode>3): Call
aarch64_output_sve_vector_inc_dec instead of
aarch64_output_sve_inc_dec_immediate.
From-SVN: r274518
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
d7a09c445a
commit
0fdc30bcf5
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@ -1,3 +1,41 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-protos.h
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(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
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(aarch64_sve_inc_dec_immediate_p): Rename to...
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(aarch64_sve_vector_inc_dec_immediate_p): ...this.
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(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
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(aarch64_output_sve_scalar_inc_dec): Declare.
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(aarch64_output_sve_inc_dec_immediate): Rename to...
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(aarch64_output_sve_vector_inc_dec): ...this.
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* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
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(aarch64_output_sve_scalar_inc_dec): New functions.
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(aarch64_output_sve_addvl_addpl): Remove the base and offset
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arguments. Only handle true ADDVL and ADDPL instructions;
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don't emit an INC or DEC.
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(aarch64_sve_inc_dec_immediate_p): Rename to...
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(aarch64_sve_vector_inc_dec_immediate_p): ...this.
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(aarch64_output_sve_inc_dec_immediate): Rename to...
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(aarch64_output_sve_vector_inc_dec): ...this. Update call to
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aarch64_sve_vector_inc_dec_immediate_p.
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* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
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(aarch64_sve_plus_immediate): New predicates.
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(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
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rather than aarch64_sve_addvl_addpl_immediate.
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(aarch64_sve_inc_dec_immediate): Rename to...
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(aarch64_sve_vector_inc_dec_immediate): ...this. Update call to
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aarch64_sve_vector_inc_dec_immediate_p.
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(aarch64_sve_add_operand): Update accordingly.
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* config/aarch64/constraints.md (Uai): New constraint.
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(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
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* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
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operand into a register if it satisfies aarch64_sve_plus_immediate.
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(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
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for Uai. Update calls to aarch64_output_sve_addvl_addpl.
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* config/aarch64/aarch64-sve.md (add<mode>3): Call
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aarch64_output_sve_vector_inc_dec instead of
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aarch64_output_sve_inc_dec_immediate.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (UNSPEC_REVB, UNSPEC_REVH)
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@ -476,8 +476,9 @@ bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
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bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
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opt_machine_mode aarch64_sve_pred_mode (unsigned int);
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bool aarch64_sve_cnt_immediate_p (rtx);
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bool aarch64_sve_scalar_inc_dec_immediate_p (rtx);
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bool aarch64_sve_addvl_addpl_immediate_p (rtx);
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bool aarch64_sve_inc_dec_immediate_p (rtx);
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bool aarch64_sve_vector_inc_dec_immediate_p (rtx);
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int aarch64_add_offset_temporaries (rtx);
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void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
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bool aarch64_mov_operand_p (rtx, machine_mode);
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@ -485,8 +486,9 @@ rtx aarch64_reverse_mask (machine_mode, unsigned int);
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bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64);
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bool aarch64_offset_9bit_signed_unscaled_p (machine_mode, poly_int64);
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char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx);
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char *aarch64_output_sve_addvl_addpl (rtx, rtx, rtx);
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char *aarch64_output_sve_inc_dec_immediate (const char *, rtx);
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char *aarch64_output_sve_scalar_inc_dec (rtx);
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char *aarch64_output_sve_addvl_addpl (rtx);
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char *aarch64_output_sve_vector_inc_dec (const char *, rtx);
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char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
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char *aarch64_output_simd_mov_immediate (rtx, unsigned,
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enum simd_immediate_check w = AARCH64_CHECK_MOV);
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@ -1971,7 +1971,7 @@
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"@
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add\t%0.<Vetype>, %0.<Vetype>, #%D2
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sub\t%0.<Vetype>, %0.<Vetype>, #%N2
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* return aarch64_output_sve_inc_dec_immediate (\"%0.<Vetype>\", operands[2]);
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* return aarch64_output_sve_vector_inc_dec (\"%0.<Vetype>\", operands[2]);
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movprfx\t%0, %1\;add\t%0.<Vetype>, %0.<Vetype>, #%D2
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movprfx\t%0, %1\;sub\t%0.<Vetype>, %0.<Vetype>, #%N2
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add\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>"
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@ -2950,6 +2950,33 @@ aarch64_output_sve_cnt_immediate (const char *prefix, const char *operands,
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value.coeffs[1], 0);
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}
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/* Return true if we can add X using a single SVE INC or DEC instruction. */
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bool
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aarch64_sve_scalar_inc_dec_immediate_p (rtx x)
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{
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poly_int64 value;
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return (poly_int_rtx_p (x, &value)
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&& (aarch64_sve_cnt_immediate_p (value)
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|| aarch64_sve_cnt_immediate_p (-value)));
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}
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/* Return the asm string for adding SVE INC/DEC immediate OFFSET to
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operand 0. */
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char *
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aarch64_output_sve_scalar_inc_dec (rtx offset)
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{
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poly_int64 offset_value = rtx_to_poly_int64 (offset);
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gcc_assert (offset_value.coeffs[0] == offset_value.coeffs[1]);
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if (offset_value.coeffs[1] > 0)
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return aarch64_output_sve_cnt_immediate ("inc", "%x0",
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offset_value.coeffs[1], 0);
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else
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return aarch64_output_sve_cnt_immediate ("dec", "%x0",
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-offset_value.coeffs[1], 0);
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}
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/* Return true if we can add VALUE to a register using a single ADDVL
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or ADDPL instruction. */
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@ -2975,27 +3002,16 @@ aarch64_sve_addvl_addpl_immediate_p (rtx x)
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&& aarch64_sve_addvl_addpl_immediate_p (value));
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}
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/* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
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and storing the result in operand 0. */
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/* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
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to operand 1 and storing the result in operand 0. */
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char *
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aarch64_output_sve_addvl_addpl (rtx dest, rtx base, rtx offset)
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aarch64_output_sve_addvl_addpl (rtx offset)
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{
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static char buffer[sizeof ("addpl\t%x0, %x1, #-") + 3 * sizeof (int)];
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poly_int64 offset_value = rtx_to_poly_int64 (offset);
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gcc_assert (aarch64_sve_addvl_addpl_immediate_p (offset_value));
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/* Use INC or DEC if possible. */
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if (rtx_equal_p (dest, base) && GP_REGNUM_P (REGNO (dest)))
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{
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if (aarch64_sve_cnt_immediate_p (offset_value))
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return aarch64_output_sve_cnt_immediate ("inc", "%x0",
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offset_value.coeffs[1], 0);
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if (aarch64_sve_cnt_immediate_p (-offset_value))
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return aarch64_output_sve_cnt_immediate ("dec", "%x0",
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-offset_value.coeffs[1], 0);
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}
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int factor = offset_value.coeffs[1];
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if ((factor & 15) == 0)
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snprintf (buffer, sizeof (buffer), "addvl\t%%x0, %%x1, #%d", factor / 16);
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@ -3010,8 +3026,8 @@ aarch64_output_sve_addvl_addpl (rtx dest, rtx base, rtx offset)
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factor in *FACTOR_OUT (if nonnull). */
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bool
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aarch64_sve_inc_dec_immediate_p (rtx x, int *factor_out,
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unsigned int *nelts_per_vq_out)
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aarch64_sve_vector_inc_dec_immediate_p (rtx x, int *factor_out,
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unsigned int *nelts_per_vq_out)
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{
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rtx elt;
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poly_int64 value;
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@ -3045,9 +3061,9 @@ aarch64_sve_inc_dec_immediate_p (rtx x, int *factor_out,
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instruction. */
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bool
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aarch64_sve_inc_dec_immediate_p (rtx x)
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aarch64_sve_vector_inc_dec_immediate_p (rtx x)
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{
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return aarch64_sve_inc_dec_immediate_p (x, NULL, NULL);
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return aarch64_sve_vector_inc_dec_immediate_p (x, NULL, NULL);
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}
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/* Return the asm template for an SVE vector INC or DEC instruction.
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@ -3055,11 +3071,11 @@ aarch64_sve_inc_dec_immediate_p (rtx x)
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value of the vector count operand itself. */
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char *
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aarch64_output_sve_inc_dec_immediate (const char *operands, rtx x)
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aarch64_output_sve_vector_inc_dec (const char *operands, rtx x)
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{
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int factor;
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unsigned int nelts_per_vq;
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if (!aarch64_sve_inc_dec_immediate_p (x, &factor, &nelts_per_vq))
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if (!aarch64_sve_vector_inc_dec_immediate_p (x, &factor, &nelts_per_vq))
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gcc_unreachable ();
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if (factor < 0)
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return aarch64_output_sve_cnt_immediate ("dec", operands, -factor,
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@ -1753,6 +1753,7 @@
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/* If the constant is too large for a single instruction and isn't frame
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based, split off the immediate so it is available for CSE. */
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if (!aarch64_plus_immediate (operands[2], <MODE>mode)
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&& !(TARGET_SVE && aarch64_sve_plus_immediate (operands[2], <MODE>mode))
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&& can_create_pseudo_p ()
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&& (!REG_P (op1)
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|| !REGNO_PTR_FRAME_P (REGNO (op1))))
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@ -1770,10 +1771,10 @@
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(define_insn "*add<mode>3_aarch64"
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[(set
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(match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r,rk")
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(match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r,r,rk")
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(plus:GPI
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(match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk,rk")
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(match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa,Uav")))]
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(match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk,0,rk")
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(match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa,Uai,Uav")))]
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""
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"@
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add\\t%<w>0, %<w>1, %2
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@ -1781,10 +1782,11 @@
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add\\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>
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sub\\t%<w>0, %<w>1, #%n2
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#
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* return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);"
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;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder.
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[(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm")
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(set_attr "arch" "*,*,simd,*,*,*")]
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* return aarch64_output_sve_scalar_inc_dec (operands[2]);
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* return aarch64_output_sve_addvl_addpl (operands[2]);"
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;; The "alu_imm" types for INC/DEC and ADDVL/ADDPL are just placeholders.
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[(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm,alu_imm")
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(set_attr "arch" "*,*,simd,*,*,sve,sve")]
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)
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;; zero_extend version of above
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@ -1863,17 +1865,18 @@
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;; this pattern.
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(define_insn_and_split "*add<mode>3_poly_1"
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[(set
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(match_operand:GPI 0 "register_operand" "=r,r,r,r,r,&r")
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(match_operand:GPI 0 "register_operand" "=r,r,r,r,r,r,&r")
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(plus:GPI
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(match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,rk,rk")
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(match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uav,Uat")))]
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(match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,rk,0,rk")
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(match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uav,Uai,Uat")))]
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"TARGET_SVE && operands[0] != stack_pointer_rtx"
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"@
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add\\t%<w>0, %<w>1, %2
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add\\t%<w>0, %<w>1, %<w>2
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sub\\t%<w>0, %<w>1, #%n2
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#
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* return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);
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* return aarch64_output_sve_scalar_inc_dec (operands[2]);
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* return aarch64_output_sve_addvl_addpl (operands[2]);
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#"
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"&& epilogue_completed
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&& !reg_overlap_mentioned_p (operands[0], operands[1])
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@ -1884,8 +1887,8 @@
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operands[2], operands[0], NULL_RTX);
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DONE;
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}
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;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder.
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[(set_attr "type" "alu_imm,alu_sreg,alu_imm,multiple,alu_imm,multiple")]
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;; The "alu_imm" types for INC/DEC and ADDVL/ADDPL are just placeholders.
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[(set_attr "type" "alu_imm,alu_sreg,alu_imm,multiple,alu_imm,alu_imm,multiple")]
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)
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(define_split
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@ -49,6 +49,12 @@
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(and (match_code "const_int")
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(match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
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(define_constraint "Uai"
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"@internal
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A constraint that matches a VG-based constant that can be added by
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a single INC or DEC."
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(match_operand 0 "aarch64_sve_scalar_inc_dec_immediate"))
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(define_constraint "Uav"
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"@internal
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A constraint that matches a VG-based constant that can be added by
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@ -416,7 +422,7 @@
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"@internal
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A constraint that matches a vector count operand valid for SVE INC and
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DEC instructions."
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(match_operand 0 "aarch64_sve_inc_dec_immediate"))
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(match_operand 0 "aarch64_sve_vector_inc_dec_immediate"))
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(define_constraint "vsn"
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"@internal
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@ -144,10 +144,18 @@
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(and (match_operand 0 "aarch64_pluslong_immediate")
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(not (match_operand 0 "aarch64_plus_immediate"))))
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(define_predicate "aarch64_sve_scalar_inc_dec_immediate"
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(and (match_code "const_poly_int")
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(match_test "aarch64_sve_scalar_inc_dec_immediate_p (op)")))
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(define_predicate "aarch64_sve_addvl_addpl_immediate"
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(and (match_code "const_poly_int")
|
||||
(match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
|
||||
|
||||
(define_predicate "aarch64_sve_plus_immediate"
|
||||
(ior (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate")
|
||||
(match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
|
||||
|
||||
(define_predicate "aarch64_split_add_offset_immediate"
|
||||
(and (match_code "const_poly_int")
|
||||
(match_test "aarch64_add_offset_temporaries (op) == 1")))
|
||||
|
|
@ -155,7 +163,8 @@
|
|||
(define_predicate "aarch64_pluslong_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "aarch64_pluslong_immediate")
|
||||
(match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
|
||||
(and (match_test "TARGET_SVE")
|
||||
(match_operand 0 "aarch64_sve_plus_immediate"))))
|
||||
|
||||
(define_predicate "aarch64_pluslong_or_poly_operand"
|
||||
(ior (match_operand 0 "aarch64_pluslong_operand")
|
||||
|
|
@ -602,9 +611,9 @@
|
|||
(and (match_code "const,const_vector")
|
||||
(match_test "aarch64_sve_arith_immediate_p (op, true)")))
|
||||
|
||||
(define_predicate "aarch64_sve_inc_dec_immediate"
|
||||
(define_predicate "aarch64_sve_vector_inc_dec_immediate"
|
||||
(and (match_code "const,const_vector")
|
||||
(match_test "aarch64_sve_inc_dec_immediate_p (op)")))
|
||||
(match_test "aarch64_sve_vector_inc_dec_immediate_p (op)")))
|
||||
|
||||
(define_predicate "aarch64_sve_uxtb_immediate"
|
||||
(and (match_code "const_vector")
|
||||
|
|
@ -687,7 +696,7 @@
|
|||
(define_predicate "aarch64_sve_add_operand"
|
||||
(ior (match_operand 0 "aarch64_sve_arith_operand")
|
||||
(match_operand 0 "aarch64_sve_sub_arith_immediate")
|
||||
(match_operand 0 "aarch64_sve_inc_dec_immediate")))
|
||||
(match_operand 0 "aarch64_sve_vector_inc_dec_immediate")))
|
||||
|
||||
(define_predicate "aarch64_sve_pred_and_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
|
|
|
|||
Loading…
Reference in New Issue