i386.md (shift_insn): Rename code attribute from shiftrt_insn.
* config/i386/i386.md (shift_insn): Rename code attribute from shiftrt_insn. Also handle ashift RTX. (shift): Rename code attribute from shiftrt. Also handle ashift RTX. (vshift): New code attribute. (<shift_insn>*): Rename from <shiftrt_insn>*. Update asm templates. (any_lshift): Move and rename code iterator from ... * config/i386/sse.md (lshift): ... here. (lshift_insn): Remove code attribute. (lshift): Remove code attribute. (vlshr<mode>3): Use lshiftrt RTX. (vashr<mode>3, ashrv16qi3, ashrv2di3): Use ashiftrt RTX. (vashl<mode>3, ashlv16qi3): Use ashift RTX. (avx2_<lshift>v<mode>): Rename from avx2_<shift_insn>v<mode>. Use any_lshift code iterator. Update asm template. (<shift_insn><mode>3): Macroize insn from lshr<mode>3 and ashl<mode>3 usign any_lshift code iterator. * config/i386/mmx.md (mmx_<shift_insn><mode>3): Macroize insn from mmx_lshr<mode>3 and mmx_ashl<mode>3 usign any_lshift code iterator. * config/i386/i386.c (bdesc_args) <__builtin_ia32_psll>: Update. From-SVN: r180624
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
18232de4db
commit
1162730f53
@ -3,15 +3,21 @@
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* config/i386/i386.md (shift_insn): Rename code attribute from
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shiftrt_insn. Also handle ashift RTX.
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(shift): Rename code attribute from shiftrt. Also handle ashift RTX.
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(vshift): New code attribute.
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(<shift_insn>*): Rename from <shiftrt_insn>*. Update asm templates.
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* config/i386/sse.md (any_lshift): Rename code iterator from lshift.
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(any_lshift): Move and rename code iterator from ...
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* config/i386/sse.md (lshift): ... here.
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(lshift_insn): Remove code attribute.
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(lshift): Remove code attribute.
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(vlshr<mode>3): Use lshiftrt RTX.
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(vashr<mode>3): Use ashiftrt RTX.
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(vashl<mode>3): Use ashift RTX.
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(vashr<mode>3, ashrv16qi3, ashrv2di3): Use ashiftrt RTX.
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(vashl<mode>3, ashlv16qi3): Use ashift RTX.
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(avx2_<lshift>v<mode>): Rename from avx2_<shift_insn>v<mode>. Use
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any_lshift code iterator. Update asm template.
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(<shift_insn><mode>3): Macroize insn from lshr<mode>3 and ashl<mode>3
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usign any_lshift code iterator.
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* config/i386/mmx.md (mmx_<shift_insn><mode>3): Macroize insn from
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mmx_lshr<mode>3 and mmx_ashl<mode>3 usign any_lshift code iterator.
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* config/i386/i386.c (bdesc_args) <__builtin_ia32_psll>: Update.
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2011-10-28 Georg-Johann Lay <avr@gjlay.de>
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@ -772,6 +772,9 @@
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;; Base name for insn mnemonic.
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(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
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;; Mapping of logic-shift operators
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(define_code_iterator any_lshift [ashift lshiftrt])
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;; Mapping of shift-right operators
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(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
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@ -781,6 +784,7 @@
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;; Base name for insn mnemonic.
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(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
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(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
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;; Mapping of rotate operators
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(define_code_iterator any_rotate [rotate rotatert])
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@ -1037,27 +1037,13 @@
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(const_string "0")))
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(set_attr "mode" "DI")])
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(define_insn "mmx_lshr<mode>3"
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(define_insn "mmx_<shift_insn><mode>3"
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[(set (match_operand:MMXMODE248 0 "register_operand" "=y")
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(lshiftrt:MMXMODE248
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(any_lshift:MMXMODE248
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(match_operand:MMXMODE248 1 "register_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "yN")))]
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"TARGET_MMX"
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"psrl<mmxvecsize>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxshft")
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(set (attr "length_immediate")
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(if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "1")
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(const_string "0")))
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(set_attr "mode" "DI")])
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(define_insn "mmx_ashl<mode>3"
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[(set (match_operand:MMXMODE248 0 "register_operand" "=y")
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(ashift:MMXMODE248
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(match_operand:MMXMODE248 1 "register_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "yN")))]
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"TARGET_MMX"
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"psll<mmxvecsize>\t{%2, %0|%0, %2}"
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"p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxshft")
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(set (attr "length_immediate")
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(if_then_else (match_operand 2 "const_int_operand" "")
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@ -167,9 +167,6 @@
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(V4SI "vec") (V8SI "avx2")
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(V2DI "vec") (V4DI "avx2")])
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;; Mapping of logic-shift operators
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(define_code_iterator any_lshift [ashift lshiftrt])
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(define_mode_attr ssedoublemode
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[(V16HI "V16SI") (V8HI "V8SI")])
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@ -5826,34 +5823,15 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "lshr<mode>3"
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(define_insn "<shift_insn><mode>3"
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[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
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(lshiftrt:VI248_AVX2
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(any_lshift:VI248_AVX2
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(match_operand:VI248_AVX2 1 "register_operand" "0,x")
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(match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
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"TARGET_SSE2"
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"@
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psrl<ssemodesuffix>\t{%2, %0|%0, %2}
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vpsrl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseishft")
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(set (attr "length_immediate")
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(if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "1")
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(const_string "0")))
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(set_attr "prefix_data16" "1,*")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "ashl<mode>3"
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[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
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(ashift:VI248_AVX2
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(match_operand:VI248_AVX2 1 "register_operand" "0,x")
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(match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
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"TARGET_SSE2"
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"@
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psll<ssemodesuffix>\t{%2, %0|%0, %2}
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vpsll<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
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v<vshift><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseishft")
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(set (attr "length_immediate")
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@ -11406,9 +11384,10 @@
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;; SSE2 doesn't have some shift varients, so define versions for XOP
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(define_expand "ashlv16qi3"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")]
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[(set (match_operand:V16QI 0 "register_operand" "")
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(ashift:V16QI
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (16);
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@ -11442,9 +11421,10 @@
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})
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(define_expand "ashrv16qi3"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")]
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[(set (match_operand:V16QI 0 "register_operand" "")
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(ashiftrt:V16QI
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (16);
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@ -11473,9 +11453,10 @@
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})
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(define_expand "ashrv2di3"
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[(match_operand:V2DI 0 "register_operand" "")
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(match_operand:V2DI 1 "register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")]
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[(set (match_operand:V2DI 0 "register_operand" "")
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(ashiftrt:V2DI
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(match_operand:V2DI 1 "register_operand" "")
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(match_operand:DI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (2);
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@ -12484,7 +12465,7 @@
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(match_operand:VI48_AVX2 1 "register_operand" "x")
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(match_operand:VI48_AVX2 2 "nonimmediate_operand" "xm")))]
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"TARGET_AVX2"
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"vp<shift>v<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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"vp<vshift>v<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sseishft")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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