* config/i386/i386.md: Move some insn patterns around.
From-SVN: r242809
This commit is contained in:
Uros Bizjak
parent
a2556bdf78
commit
11a669fbeb
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@ -6738,19 +6738,6 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*add<mode>3_cconly_overflow_2"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "%0")
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(match_operand:SWI 2 "<general_operand>" "<g>"))
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(match_dup 2)))
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(clobber (match_scratch:SWI 0 "=<r>"))]
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"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"add{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*add<mode>3_cc_overflow_1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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@ -6765,20 +6752,6 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*add<mode>3_cc_overflow_2"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
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(match_dup 2)))
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(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
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(plus:SWI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
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"add{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*addsi3_zext_cc_overflow_1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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@ -6793,6 +6766,33 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*add<mode>3_cconly_overflow_2"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "%0")
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(match_operand:SWI 2 "<general_operand>" "<g>"))
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(match_dup 2)))
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(clobber (match_scratch:SWI 0 "=<r>"))]
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"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"add{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*add<mode>3_cc_overflow_2"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
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(match_dup 2)))
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(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
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(plus:SWI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
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"add{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*addsi3_zext_cc_overflow_2"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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@ -7337,30 +7337,6 @@
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(set_attr "bdver1_decode" "direct")
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(set_attr "mode" "DI")])
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(define_insn "*<s>mulsi3_highpart_1"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI
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(any_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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(any_extend:DI
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=1"))
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(clobber (reg:CC FLAGS_REG))]
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"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"<sgnprefix>mul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set (attr "athlon_decode")
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(if_then_else (eq_attr "cpu" "athlon")
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(const_string "vector")
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(const_string "double")))
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(set_attr "amdfam10_decode" "double")
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(set_attr "bdver1_decode" "direct")
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(set_attr "mode" "SI")])
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(define_insn "*<s>mulsi3_highpart_zext"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(zero_extend:DI (truncate:SI
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@ -7385,6 +7361,30 @@
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(set_attr "bdver1_decode" "direct")
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(set_attr "mode" "SI")])
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(define_insn "*<s>mulsi3_highpart_1"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI
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(any_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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(any_extend:DI
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=1"))
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(clobber (reg:CC FLAGS_REG))]
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"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"<sgnprefix>mul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set (attr "athlon_decode")
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(if_then_else (eq_attr "cpu" "athlon")
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(const_string "vector")
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(const_string "double")))
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(set_attr "amdfam10_decode" "double")
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(set_attr "bdver1_decode" "direct")
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(set_attr "mode" "SI")])
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;; The patterns that match these are at the end of this file.
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(define_expand "mulxf3"
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@ -8217,6 +8217,18 @@
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(const_string "*")))
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(set_attr "mode" "SI,DI,DI,SI,DI")])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*andsi_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
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"and{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*andsi_1"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
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(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm,k")
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@ -8248,18 +8260,6 @@
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(set_attr "length_immediate" "*,*,0,0")
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(set_attr "mode" "SI")])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*andsi_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
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"and{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*andhi_1"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya,!k")
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(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm,k")
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@ -8514,6 +8514,21 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "SI,DI,DI")])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*andsi_2_zext"
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[(set (reg FLAGS_REG)
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(compare (and:SI
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(match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
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"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
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&& ix86_binary_operator_ok (AND, SImode, operands)"
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"and{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*andqi_2_maybe_si"
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[(set (reg FLAGS_REG)
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(compare (and:QI
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@ -8552,21 +8567,6 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*andsi_2_zext"
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[(set (reg FLAGS_REG)
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(compare (and:SI
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(match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
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"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
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&& ix86_binary_operator_ok (AND, SImode, operands)"
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"and{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*andqi_2_slp"
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[(set (reg FLAGS_REG)
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(compare (and:QI
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@ -8785,6 +8785,29 @@
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[(set_attr "type" "alu,alu,msklog")
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(set_attr "mode" "<MODE>")])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*<code>si_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
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"<logic>{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*<code>si_1_zext_imm"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(any_or:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
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(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
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"<logic>{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*<code>hi_1"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k")
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(any_or:HI
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@ -8818,29 +8841,6 @@
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(symbol_ref "!TARGET_PARTIAL_REG_STALL")]
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(symbol_ref "true")))])
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;; See comment for addsi_1_zext why we do use nonimmediate_operand
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(define_insn "*<code>si_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
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"<logic>{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*<code>si_1_zext_imm"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(any_or:DI
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(zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
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(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
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"<logic>{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*<code>qi_1_slp"
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[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
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(any_or:QI (match_dup 0)
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@ -8866,111 +8866,6 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "kxnor<mode>"
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[(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=r,!k")
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(not:SWI1248_AVX512BW
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(xor:SWI1248_AVX512BW
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(match_operand:SWI1248_AVX512BW 1 "register_operand" "0,k")
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(match_operand:SWI1248_AVX512BW 2 "register_operand" "r,k"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F"
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{
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if (which_alternative == 0)
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return "#";
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if (get_attr_mode (insn) == MODE_HI)
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return "kxnorw\t{%2, %1, %0|%0, %1, %2}";
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else
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return "kxnor<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
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}
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[(set_attr "type" "*,msklog")
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(set_attr "prefix" "*,vex")
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(set (attr "mode")
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(cond [(and (eq_attr "alternative" "1")
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(and (match_test "<MODE>mode == QImode")
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(not (match_test "TARGET_AVX512DQ"))))
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(const_string "HI")
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]
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(const_string "<MODE>")))])
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(define_split
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[(set (match_operand:SWI1248x 0 "general_reg_operand")
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(not:SWI1248x
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(xor:SWI1248x
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(match_dup 0)
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(match_operand:SWI1248x 1 "general_reg_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_AVX512F && reload_completed"
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[(parallel [(set (match_dup 0)
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(xor:SWI1248x (match_dup 0)
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(match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 0)
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(not:SWI1248x (match_dup 0)))])
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;;There are kortrest[bdq] but no intrinsics for them.
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;;We probably don't need to implement them.
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(define_insn "kortestzhi"
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[(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(ior:HI
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(match_operand:HI 0 "register_operand" "k")
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(match_operand:HI 1 "register_operand" "k"))
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(const_int 0)))]
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"TARGET_AVX512F && ix86_match_ccmode (insn, CCZmode)"
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"kortestw\t{%1, %0|%0, %1}"
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[(set_attr "mode" "HI")
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(set_attr "type" "msklog")
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(set_attr "prefix" "vex")])
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(define_insn "kortestchi"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(ior:HI
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(match_operand:HI 0 "register_operand" "k")
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(match_operand:HI 1 "register_operand" "k"))
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(const_int -1)))]
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"TARGET_AVX512F && ix86_match_ccmode (insn, CCCmode)"
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"kortestw\t{%1, %0|%0, %1}"
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[(set_attr "mode" "HI")
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(set_attr "type" "msklog")
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(set_attr "prefix" "vex")])
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(define_insn "kunpckhi"
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[(set (match_operand:HI 0 "register_operand" "=k")
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(ior:HI
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(ashift:HI
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(zero_extend:HI (match_operand:QI 1 "register_operand" "k"))
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(const_int 8))
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(zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))]
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"TARGET_AVX512F"
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"kunpckbw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "mode" "HI")
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(set_attr "type" "msklog")
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(set_attr "prefix" "vex")])
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(define_insn "kunpcksi"
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[(set (match_operand:SI 0 "register_operand" "=k")
|
||||
(ior:SI
|
||||
(ashift:SI
|
||||
(zero_extend:SI (match_operand:HI 1 "register_operand" "k"))
|
||||
(const_int 16))
|
||||
(zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))]
|
||||
"TARGET_AVX512BW"
|
||||
"kunpckwd\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "kunpckdi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=k")
|
||||
(ior:DI
|
||||
(ashift:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "register_operand" "k"))
|
||||
(const_int 32))
|
||||
(zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))]
|
||||
"TARGET_AVX512BW"
|
||||
"kunpckdq\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "mode" "DI")])
|
||||
|
||||
;; See comment for addsi_1_zext why we do use nonimmediate_operand
|
||||
;; ??? Special case for immediate operand is missing - it is tricky.
|
||||
(define_insn "*<code>si_2_zext"
|
||||
|
|
@ -9170,6 +9065,111 @@
|
|||
(set_attr "type" "alu")
|
||||
(set_attr "modrm" "1")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "kxnor<mode>"
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=r,!k")
|
||||
(not:SWI1248_AVX512BW
|
||||
(xor:SWI1248_AVX512BW
|
||||
(match_operand:SWI1248_AVX512BW 1 "register_operand" "0,k")
|
||||
(match_operand:SWI1248_AVX512BW 2 "register_operand" "r,k"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_AVX512F"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return "#";
|
||||
|
||||
if (get_attr_mode (insn) == MODE_HI)
|
||||
return "kxnorw\t{%2, %1, %0|%0, %1, %2}";
|
||||
else
|
||||
return "kxnor<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
|
||||
}
|
||||
[(set_attr "type" "*,msklog")
|
||||
(set_attr "prefix" "*,vex")
|
||||
(set (attr "mode")
|
||||
(cond [(and (eq_attr "alternative" "1")
|
||||
(and (match_test "<MODE>mode == QImode")
|
||||
(not (match_test "TARGET_AVX512DQ"))))
|
||||
(const_string "HI")
|
||||
]
|
||||
(const_string "<MODE>")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SWI1248x 0 "general_reg_operand")
|
||||
(not:SWI1248x
|
||||
(xor:SWI1248x
|
||||
(match_dup 0)
|
||||
(match_operand:SWI1248x 1 "general_reg_operand"))))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_AVX512F && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(xor:SWI1248x (match_dup 0)
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(set (match_dup 0)
|
||||
(not:SWI1248x (match_dup 0)))])
|
||||
|
||||
;;There are kortrest[bdq] but no intrinsics for them.
|
||||
;;We probably don't need to implement them.
|
||||
(define_insn "kortestzhi"
|
||||
[(set (reg:CCZ FLAGS_REG)
|
||||
(compare:CCZ
|
||||
(ior:HI
|
||||
(match_operand:HI 0 "register_operand" "k")
|
||||
(match_operand:HI 1 "register_operand" "k"))
|
||||
(const_int 0)))]
|
||||
"TARGET_AVX512F && ix86_match_ccmode (insn, CCZmode)"
|
||||
"kortestw\t{%1, %0|%0, %1}"
|
||||
[(set_attr "mode" "HI")
|
||||
(set_attr "type" "msklog")
|
||||
(set_attr "prefix" "vex")])
|
||||
|
||||
(define_insn "kortestchi"
|
||||
[(set (reg:CCC FLAGS_REG)
|
||||
(compare:CCC
|
||||
(ior:HI
|
||||
(match_operand:HI 0 "register_operand" "k")
|
||||
(match_operand:HI 1 "register_operand" "k"))
|
||||
(const_int -1)))]
|
||||
"TARGET_AVX512F && ix86_match_ccmode (insn, CCCmode)"
|
||||
"kortestw\t{%1, %0|%0, %1}"
|
||||
[(set_attr "mode" "HI")
|
||||
(set_attr "type" "msklog")
|
||||
(set_attr "prefix" "vex")])
|
||||
|
||||
(define_insn "kunpckhi"
|
||||
[(set (match_operand:HI 0 "register_operand" "=k")
|
||||
(ior:HI
|
||||
(ashift:HI
|
||||
(zero_extend:HI (match_operand:QI 1 "register_operand" "k"))
|
||||
(const_int 8))
|
||||
(zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))]
|
||||
"TARGET_AVX512F"
|
||||
"kunpckbw\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "mode" "HI")
|
||||
(set_attr "type" "msklog")
|
||||
(set_attr "prefix" "vex")])
|
||||
|
||||
(define_insn "kunpcksi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=k")
|
||||
(ior:SI
|
||||
(ashift:SI
|
||||
(zero_extend:SI (match_operand:HI 1 "register_operand" "k"))
|
||||
(const_int 16))
|
||||
(zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))]
|
||||
"TARGET_AVX512BW"
|
||||
"kunpckwd\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "kunpckdi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=k")
|
||||
(ior:DI
|
||||
(ashift:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "register_operand" "k"))
|
||||
(const_int 32))
|
||||
(zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))]
|
||||
"TARGET_AVX512BW"
|
||||
"kunpckdq\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "mode" "DI")])
|
||||
|
||||
;; Negation instructions
|
||||
|
||||
|
|
@ -9578,6 +9578,16 @@
|
|||
(set_attr "prefix" "*,vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; ??? Currently never generated - xor is used instead.
|
||||
(define_insn "*one_cmplsi2_1_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(zero_extend:DI
|
||||
(not:SI (match_operand:SI 1 "register_operand" "0"))))]
|
||||
"TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
|
||||
"not{l}\t%k0"
|
||||
[(set_attr "type" "negnot")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*one_cmplhi2_1"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,!k")
|
||||
(not:HI (match_operand:HI 1 "nonimmediate_operand" "0,k")))]
|
||||
|
|
@ -9626,16 +9636,6 @@
|
|||
(symbol_ref "!TARGET_PARTIAL_REG_STALL")]
|
||||
(symbol_ref "true")))])
|
||||
|
||||
;; ??? Currently never generated - xor is used instead.
|
||||
(define_insn "*one_cmplsi2_1_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(zero_extend:DI
|
||||
(not:SI (match_operand:SI 1 "register_operand" "0"))))]
|
||||
"TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
|
||||
"not{l}\t%k0"
|
||||
[(set_attr "type" "negnot")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*one_cmpl<mode>2_2"
|
||||
[(set (reg FLAGS_REG)
|
||||
(compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
|
||||
|
|
@ -10442,23 +10442,6 @@
|
|||
(set_attr "modrm" "0,1")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "ashrsi3_cvt"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
|
||||
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
|
||||
(match_operand:QI 2 "const_int_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"INTVAL (operands[2]) == 31
|
||||
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
|
||||
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
|
||||
"@
|
||||
{cltd|cdq}
|
||||
sar{l}\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "imovx,ishift")
|
||||
(set_attr "prefix_0f" "0,*")
|
||||
(set_attr "length_immediate" "0,*")
|
||||
(set_attr "modrm" "0,1")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*ashrsi3_cvt_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=*d,r")
|
||||
(zero_extend:DI
|
||||
|
|
@ -10477,6 +10460,23 @@
|
|||
(set_attr "modrm" "0,1")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "ashrsi3_cvt"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
|
||||
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
|
||||
(match_operand:QI 2 "const_int_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"INTVAL (operands[2]) == 31
|
||||
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
|
||||
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
|
||||
"@
|
||||
{cltd|cdq}
|
||||
sar{l}\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "imovx,ishift")
|
||||
(set_attr "prefix_0f" "0,*")
|
||||
(set_attr "length_immediate" "0,*")
|
||||
(set_attr "modrm" "0,1")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "x86_shift<mode>_adj_3"
|
||||
[(use (match_operand:SWI48 0 "register_operand"))
|
||||
(use (match_operand:SWI48 1 "register_operand"))
|
||||
|
|
|
|||
Loading…
Reference in New Issue