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re PR target/68609 (PowerPC reciprocal estimate missed opportunities) 

PR target/68609
        * config/rs6000/rs6000.c (rs6000_emit_swsqrt): Add vector sqrt
        domain check.
        * config/rs6000/vector.md (sqrt<mode>2): Call rs6000_emit_swsqrt
        for V4SFmode.

From-SVN: r232632
This commit is contained in:
David Edelsohn 2016-01-20 19:39:08 +00:00 committed by David Edelsohn
parent b1de98e3d9
commit 11c7bfe673
3 changed files with 32 additions and 6 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2016-01-20 David Edelsohn <dje.gcc@gmail.com>
PR target/68609
* config/rs6000/rs6000.c (rs6000_emit_swsqrt): Add vector sqrt
domain check.
* config/rs6000/vector.md (sqrt<mode>2): Call rs6000_emit_swsqrt
for V4SFmode.
2016-01-20 Richard Henderson <rth@redhat.com>
PR bootstrap/69343
@ -43,7 +51,7 @@
(pc_or_label_operand): New predicate.
* config/m68k/m68k.md: Add new peephole2 patterns for GTU/LEU
tests for small integers that are 2^n - 1.
2016-01-20 Jonathan Wakely <jwakely@redhat.com>
* doc/invoke.texi (Options Summary): Add '.' after @xref.

17
gcc/config/rs6000/rs6000.c
View File

@ -32904,10 +32904,19 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
if (!recip)
{
rtx zero = force_reg (mode, CONST0_RTX (mode));
rtx target = emit_conditional_move (e, GT, src, zero, mode,
e, zero, mode, 0);
if (target != e)
emit_move_insn (e, target);
if (mode == SFmode)
{
rtx target = emit_conditional_move (e, GT, src, zero, mode,
e, zero, mode, 0);
if (target != e)
emit_move_insn (e, target);
}
else
{
rtx cond = gen_rtx_GT (VOIDmode, e, zero);
rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
}
}
/* g = sqrt estimate. */

11
gcc/config/rs6000/vector.md
View File

@ -270,7 +270,16 @@
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"")
{
if (<MODE>mode == V4SFmode
&& !optimize_function_for_size_p (cfun)
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
rs6000_emit_swsqrt (operands[0], operands[1], 0);
DONE;
}
})
(define_expand "rsqrte<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")