re PR target/5626 (gcc-3.1 on sparcv9 does not generate code for long jumps)
PR target/5626 * config/sparc/sparc.md (normal_branch, inverted_branch, normal_fp_branch, inverted_fp_branch, normal_fpe_branch, inverted_fp_branch): Adjust calls to output_cbranch. Set length attribute. (normal_int_branch_sp64, inverted_int_branch_sp64): Adjust calls to output_v9branch. Set length attribute. * config/sparc/sparc.c (fcc0_reg_operand, noov_compare64_op): New predicates. (noov_compare_op): Handle CCX_NOOVmode the same way as CC_NOOVmode. (output_cbranch): Likewise. Handle far branches. (output_v9branch): Handle far branches. * config/sparc/sparc-protos.h (output_cbranch, output_v9branch): Adjust prototypes. * config/sparc/sparc.h (PREDICATE_CODES): Add fcc0_reg_operand and noov_compare64_op predicates. From-SVN: r50752
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
f846990f0c
commit
126ccea26e
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@ -1,3 +1,22 @@
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2002-03-13 Jakub Jelinek <jakub@redhat.com>
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PR target/5626
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* config/sparc/sparc.md (normal_branch, inverted_branch,
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normal_fp_branch, inverted_fp_branch, normal_fpe_branch,
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inverted_fp_branch): Adjust calls to output_cbranch.
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Set length attribute.
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(normal_int_branch_sp64, inverted_int_branch_sp64): Adjust calls to
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output_v9branch. Set length attribute.
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* config/sparc/sparc.c (fcc0_reg_operand, noov_compare64_op): New
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predicates.
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(noov_compare_op): Handle CCX_NOOVmode the same way as CC_NOOVmode.
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(output_cbranch): Likewise. Handle far branches.
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(output_v9branch): Handle far branches.
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* config/sparc/sparc-protos.h (output_cbranch, output_v9branch):
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Adjust prototypes.
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* config/sparc/sparc.h (PREDICATE_CODES): Add fcc0_reg_operand and
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noov_compare64_op predicates.
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2002-03-13 Jason Merrill <jason@redhat.com>
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* gthr-posix.h (__gthread_active_p): Move __gthread_active_ptr
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@ -85,10 +85,11 @@ extern void sparc_emit_set_const64 PARAMS ((rtx, rtx));
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extern void sparc_emit_set_symbolic_const64 PARAMS ((rtx, rtx, rtx));
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extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
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extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
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extern char *output_cbranch PARAMS ((rtx, int, int, int, int, rtx));
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extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
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extern const char *output_return PARAMS ((rtx *));
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extern const char *output_sibcall PARAMS ((rtx, rtx));
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extern char *output_v9branch PARAMS ((rtx, int, int, int, int, int, rtx));
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extern char *output_v9branch PARAMS ((rtx, rtx, int, int, int, int, int,
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rtx));
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extern void emit_v9_brxx_insn PARAMS ((enum rtx_code, rtx, rtx));
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extern void print_operand PARAMS ((FILE *, rtx, int));
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extern int mems_ok_for_ldd_peep PARAMS ((rtx, rtx, rtx));
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@ -608,6 +608,27 @@ fcc_reg_operand (op, mode)
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#endif
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}
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/* Nonzero if OP is a floating point condition code fcc0 register. */
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int
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fcc0_reg_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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/* This can happen when recog is called from combine. Op may be a MEM.
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Fail instead of calling abort in this case. */
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if (GET_CODE (op) != REG)
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return 0;
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if (mode != VOIDmode && mode != GET_MODE (op))
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return 0;
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if (mode == VOIDmode
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&& (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
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return 0;
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return REGNO (op) == SPARC_FCC_REG;
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}
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/* Nonzero if OP is an integer or floating point condition code register. */
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int
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@ -878,12 +899,35 @@ noov_compare_op (op, mode)
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if (GET_RTX_CLASS (code) != '<')
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
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if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
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|| GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
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/* These are the only branches which work with CC_NOOVmode. */
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return (code == EQ || code == NE || code == GE || code == LT);
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return 1;
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}
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/* Return 1 if this is a 64-bit comparison operator. This allows the use of
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MATCH_OPERATOR to recognize all the branch insns. */
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int
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noov_compare64_op (op, mode)
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register rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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enum rtx_code code = GET_CODE (op);
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if (! TARGET_V9)
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return 0;
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if (GET_RTX_CLASS (code) != '<')
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return 0;
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if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
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/* These are the only branches which work with CCX_NOOVmode. */
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return (code == EQ || code == NE || code == GE || code == LT);
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return (GET_MODE (XEXP (op, 0)) == CCXmode);
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}
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/* Nonzero if OP is a comparison operator suitable for use in v9
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conditional move or branch on register contents instructions. */
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@ -4996,25 +5040,43 @@ sparc_va_arg (valist, type)
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INSN, if set, is the insn. */
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char *
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output_cbranch (op, label, reversed, annul, noop, insn)
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rtx op;
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output_cbranch (op, dest, label, reversed, annul, noop, insn)
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rtx op, dest;
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int label;
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int reversed, annul, noop;
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rtx insn;
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{
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static char string[32];
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static char string[50];
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enum rtx_code code = GET_CODE (op);
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rtx cc_reg = XEXP (op, 0);
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enum machine_mode mode = GET_MODE (cc_reg);
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static char v8_labelno[] = "%lX";
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static char v9_icc_labelno[] = "%%icc, %lX";
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static char v9_xcc_labelno[] = "%%xcc, %lX";
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static char v9_fcc_labelno[] = "%%fccX, %lY";
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char *labelno;
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const char *branch;
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int labeloff, spaces = 8;
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const char *labelno, *branch;
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int spaces = 8, far;
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char *p;
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if (reversed)
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/* v9 branches are limited to +-1MB. If it is too far away,
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change
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bne,pt %xcc, .LC30
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to
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be,pn %xcc, .+12
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nop
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ba .LC30
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and
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fbne,a,pn %fcc2, .LC29
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to
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fbe,pt %fcc2, .+16
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nop
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ba .LC29 */
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far = get_attr_length (insn) >= 3;
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if (reversed ^ far)
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{
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/* Reversal of FP compares takes care -- an ordered compare
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becomes an unordered compare and vice versa. */
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@ -5097,7 +5159,7 @@ output_cbranch (op, label, reversed, annul, noop, insn)
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branch = "be";
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break;
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case GE:
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if (mode == CC_NOOVmode)
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if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
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branch = "bpos";
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else
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branch = "bge";
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@ -5109,7 +5171,7 @@ output_cbranch (op, label, reversed, annul, noop, insn)
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branch = "ble";
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break;
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case LT:
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if (mode == CC_NOOVmode)
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if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
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branch = "bneg";
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else
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branch = "bl";
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@ -5133,54 +5195,89 @@ output_cbranch (op, label, reversed, annul, noop, insn)
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strcpy (string, branch);
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}
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spaces -= strlen (branch);
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p = strchr (string, '\0');
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/* Now add the annulling, the label, and a possible noop. */
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if (annul)
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if (annul && ! far)
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{
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strcat (string, ",a");
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strcpy (p, ",a");
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p += 2;
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spaces -= 2;
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}
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if (! TARGET_V9)
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{
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labeloff = 2;
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labelno = v8_labelno;
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}
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labelno = "";
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else
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{
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rtx note;
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int v8 = 0;
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if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
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if (! far && insn && INSN_ADDRESSES_SET_P ())
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{
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strcat (string,
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INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
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spaces -= 3;
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int delta = (INSN_ADDRESSES (INSN_UID (dest))
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- INSN_ADDRESSES (INSN_UID (insn)));
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/* Leave some instructions for "slop". */
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if (delta < -260000 || delta >= 260000)
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v8 = 1;
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}
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labeloff = 9;
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if (mode == CCFPmode || mode == CCFPEmode)
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{
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labeloff = 10;
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labelno = v9_fcc_labelno;
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static char v9_fcc_labelno[] = "%%fccX, ";
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/* Set the char indicating the number of the fcc reg to use. */
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labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
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v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
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labelno = v9_fcc_labelno;
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if (v8)
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{
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if (REGNO (cc_reg) == SPARC_FCC_REG)
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labelno = "";
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else
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abort ();
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}
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}
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else if (mode == CCXmode || mode == CCX_NOOVmode)
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labelno = v9_xcc_labelno;
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{
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labelno = "%%xcc, ";
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if (v8)
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abort ();
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}
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else
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labelno = v9_icc_labelno;
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{
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labelno = "%%icc, ";
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if (v8)
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labelno = "";
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}
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if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
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{
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strcpy (p,
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(((INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely) != 0) ^ far)
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? ",pt" : ",pn");
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p += 3;
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spaces -= 3;
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}
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}
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if (spaces > 0)
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*p++ = '\t';
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else
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*p++ = ' ';
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strcpy (p, labelno);
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p = strchr (p, '\0');
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if (far)
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{
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strcpy (p, ".+12\n\tnop\n\tb\t");
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if (annul || noop)
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p[3] = '6';
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p += 13;
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}
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*p++ = '%';
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*p++ = 'l';
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/* Set the char indicating the number of the operand containing the
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label_ref. */
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labelno[labeloff] = label + '0';
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if (spaces > 0)
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strcat (string, "\t");
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else
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strcat (string, " ");
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strcat (string, labelno);
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*p++ = label + '0';
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*p = '\0';
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if (noop)
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strcat (string, "\n\tnop");
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strcpy (p, "\n\tnop");
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return string;
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}
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@ -5338,22 +5435,45 @@ sparc_emit_float_lib_cmp (x, y, comparison)
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NOOP is non-zero if we have to follow this branch by a noop. */
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char *
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output_v9branch (op, reg, label, reversed, annul, noop, insn)
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rtx op;
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output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
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rtx op, dest;
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int reg, label;
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int reversed, annul, noop;
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rtx insn;
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{
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static char string[20];
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static char string[50];
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enum rtx_code code = GET_CODE (op);
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enum machine_mode mode = GET_MODE (XEXP (op, 0));
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static char labelno[] = "%X, %lX";
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rtx note;
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int spaces = 8;
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int far;
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char *p;
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/* branch on register are limited to +-128KB. If it is too far away,
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change
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brnz,pt %g1, .LC30
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to
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brz,pn %g1, .+12
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nop
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ba,pt %xcc, .LC30
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and
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brgez,a,pn %o1, .LC29
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to
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brlz,pt %o1, .+16
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nop
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ba,pt %xcc, .LC29 */
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far = get_attr_length (insn) >= 3;
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/* If not floating-point or if EQ or NE, we can just reverse the code. */
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if (reversed)
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code = reverse_condition (code), reversed = 0;
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if (reversed ^ far)
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code = reverse_condition (code);
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/* Only 64 bit versions of these instructions exist. */
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if (mode != DImode)
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@ -5365,62 +5485,90 @@ output_v9branch (op, reg, label, reversed, annul, noop, insn)
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{
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case NE:
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strcpy (string, "brnz");
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spaces -= 4;
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break;
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case EQ:
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strcpy (string, "brz");
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spaces -= 3;
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break;
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case GE:
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strcpy (string, "brgez");
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spaces -= 5;
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break;
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case LT:
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strcpy (string, "brlz");
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spaces -= 4;
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break;
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case LE:
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strcpy (string, "brlez");
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spaces -= 5;
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break;
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case GT:
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strcpy (string, "brgz");
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spaces -= 4;
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break;
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default:
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abort ();
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}
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p = strchr (string, '\0');
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/* Now add the annulling, reg, label, and nop. */
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if (annul)
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if (annul && ! far)
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{
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strcat (string, ",a");
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spaces -= 2;
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strcpy (p, ",a");
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p += 2;
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}
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if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
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{
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strcat (string,
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INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
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spaces -= 3;
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strcpy (p,
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(((INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely) != 0) ^ far)
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? ",pt" : ",pn");
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p += 3;
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}
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labelno[1] = reg + '0';
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labelno[6] = label + '0';
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if (spaces > 0)
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strcat (string, "\t");
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else
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strcat (string, " ");
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strcat (string, labelno);
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*p = p < string + 8 ? '\t' : ' ';
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p++;
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*p++ = '%';
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*p++ = '0' + reg;
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*p++ = ',';
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*p++ = ' ';
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if (far)
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{
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int veryfar = 1, delta;
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if (INSN_ADDRESSES_SET_P ())
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{
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delta = (INSN_ADDRESSES (INSN_UID (dest))
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- INSN_ADDRESSES (INSN_UID (insn)));
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/* Leave some instructions for "slop". */
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if (delta >= -260000 && delta < 260000)
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veryfar = 0;
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}
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strcpy (p, ".+12\n\tnop\n\t");
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if (annul || noop)
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p[3] = '6';
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p += 11;
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if (veryfar)
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{
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strcpy (p, "b\t");
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p += 2;
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}
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else
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{
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strcpy (p, "ba,pt\t%%xcc, ");
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p += 13;
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}
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}
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*p++ = '%';
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*p++ = 'l';
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*p++ = '0' + label;
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*p = '\0';
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if (noop)
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strcat (string, "\n\tnop");
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strcpy (p, "\n\tnop");
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return string;
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}
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|
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@ -2986,6 +2986,7 @@ do { \
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{"fp_zero_operand", {CONST_DOUBLE}}, \
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{"intreg_operand", {SUBREG, REG}}, \
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{"fcc_reg_operand", {REG}}, \
|
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{"fcc0_reg_operand", {REG}}, \
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{"icc_or_fcc_reg_operand", {REG}}, \
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{"restore_operand", {REG}}, \
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{"call_operand", {MEM}}, \
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|
|
@ -3003,6 +3004,7 @@ do { \
|
|||
{"eq_or_neq", {EQ, NE}}, \
|
||||
{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
|
||||
{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
|
||||
{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
|
||||
{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
|
||||
{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
|
||||
{"cc_arithop", {AND, IOR, XOR}}, \
|
||||
|
|
|
|||
|
|
@ -1893,11 +1893,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[0], 1, 0,
|
||||
return output_cbranch (operands[0], operands[1], 1, 0,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "noov_compare64_op" "")
|
||||
(if_then_else (lt (pc) (match_dup 1))
|
||||
(if_then_else (lt (minus (match_dup 1) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 1))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))
|
||||
(const_int 1)))])
|
||||
|
||||
;; XXX fpcmp nop braindamage
|
||||
(define_insn "*inverted_branch"
|
||||
|
|
@ -1909,11 +1921,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[0], 1, 1,
|
||||
return output_cbranch (operands[0], operands[1], 1, 1,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "noov_compare64_op" "")
|
||||
(if_then_else (lt (pc) (match_dup 1))
|
||||
(if_then_else (lt (minus (match_dup 1) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 1))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))
|
||||
(const_int 1)))])
|
||||
|
||||
;; XXX fpcmp nop braindamage
|
||||
(define_insn "*normal_fp_branch"
|
||||
|
|
@ -1926,11 +1950,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[1], 2, 0,
|
||||
return output_cbranch (operands[1], operands[2], 2, 0,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "fcc0_reg_operand" "")
|
||||
(const_int 1)
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))))])
|
||||
|
||||
;; XXX fpcmp nop braindamage
|
||||
(define_insn "*inverted_fp_branch"
|
||||
|
|
@ -1943,11 +1979,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[1], 2, 1,
|
||||
return output_cbranch (operands[1], operands[2], 2, 1,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "fcc0_reg_operand" "")
|
||||
(const_int 1)
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))))])
|
||||
|
||||
;; XXX fpcmp nop braindamage
|
||||
(define_insn "*normal_fpe_branch"
|
||||
|
|
@ -1960,11 +2008,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[1], 2, 0,
|
||||
return output_cbranch (operands[1], operands[2], 2, 0,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "fcc0_reg_operand" "")
|
||||
(const_int 1)
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))))])
|
||||
|
||||
;; XXX fpcmp nop braindamage
|
||||
(define_insn "*inverted_fpe_branch"
|
||||
|
|
@ -1977,11 +2037,23 @@
|
|||
""
|
||||
"*
|
||||
{
|
||||
return output_cbranch (operands[1], 2, 1,
|
||||
return output_cbranch (operands[1], operands[2], 2, 1,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (match_operand 0 "fcc0_reg_operand" "")
|
||||
(const_int 1)
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 260000))
|
||||
(const_int 1)
|
||||
(const_int 3)))))])
|
||||
|
||||
;; Sparc V9-specific jump insns. None of these are guaranteed to be
|
||||
;; in the architecture.
|
||||
|
|
@ -1999,11 +2071,21 @@
|
|||
"TARGET_ARCH64"
|
||||
"*
|
||||
{
|
||||
return output_v9branch (operands[0], 1, 2, 0,
|
||||
return output_v9branch (operands[0], operands[2], 1, 2, 0,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 32000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 32000))
|
||||
(const_int 1)
|
||||
(const_int 3))))])
|
||||
|
||||
;; XXX
|
||||
(define_insn "*inverted_int_branch_sp64"
|
||||
|
|
@ -2016,11 +2098,21 @@
|
|||
"TARGET_ARCH64"
|
||||
"*
|
||||
{
|
||||
return output_v9branch (operands[0], 1, 2, 1,
|
||||
return output_v9branch (operands[0], operands[2], 1, 2, 1,
|
||||
final_sequence && INSN_ANNULLED_BRANCH_P (insn),
|
||||
! final_sequence, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
(if_then_else (lt (pc) (match_dup 2))
|
||||
(if_then_else (lt (minus (match_dup 2) (pc))
|
||||
(const_int 32000))
|
||||
(const_int 1)
|
||||
(const_int 3))
|
||||
(if_then_else (lt (minus (pc) (match_dup 2))
|
||||
(const_int 32000))
|
||||
(const_int 1)
|
||||
(const_int 3))))])
|
||||
|
||||
;; Load program counter insns.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue