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sync.md (atomic_loaddi_1): Disable predication for arm_restrict_it.

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2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/sync.md (atomic_loaddi_1):
	Disable predication for arm_restrict_it.
	(arm_load_exclusive<mode>): Likewise.
	(arm_load_exclusivesi): Likewise.
	(arm_load_exclusivedi): Likewise.
	(arm_load_acquire_exclusive<mode>): Likewise.
	(arm_load_acquire_exclusivesi): Likewise.
	(arm_load_acquire_exclusivedi): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_release_exclusivedi): Likewise.
	(arm_store_release_exclusive<mode>): Likewise.

From-SVN: r199733
This commit is contained in:
Kyrylo Tkachov 2013-06-06 12:59:04 +00:00 committed by Kyrylo Tkachov
parent 15d16c8aeb
commit 12b4e7ef74
2 changed files with 35 additions and 10 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/sync.md (atomic_loaddi_1):
Disable predication for arm_restrict_it.
(arm_load_exclusive<mode>): Likewise.
(arm_load_exclusivesi): Likewise.
(arm_load_exclusivedi): Likewise.
(arm_load_acquire_exclusive<mode>): Likewise.
(arm_load_acquire_exclusivesi): Likewise.
(arm_load_acquire_exclusivedi): Likewise.
(arm_store_exclusive<mode>): Likewise.
(arm_store_exclusive<mode>): Likewise.
(arm_store_release_exclusivedi): Likewise.
(arm_store_release_exclusive<mode>): Likewise.
2013-06-06 Richard Biener <rguenther@suse.de> 2013-06-06 Richard Biener <rguenther@suse.de>
* lto-streamer.h (enum LTO_tags): Move LTO_tree_pickle_reference * lto-streamer.h (enum LTO_tags): Move LTO_tree_pickle_reference

30
gcc/config/arm/sync.md
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@ -124,7 +124,8 @@
UNSPEC_LL))] UNSPEC_LL))]
"TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN"
"ldrexd%?\t%0, %H0, %C1" "ldrexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_expand "atomic_compare_and_swap<mode>" (define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "s_register_operand" "") ;; bool out [(match_operand:SI 0 "s_register_operand" "") ;; bool out
@ -361,7 +362,8 @@
VUNSPEC_LL)))] VUNSPEC_LL)))]
"TARGET_HAVE_LDREXBH" "TARGET_HAVE_LDREXBH"
"ldrex<sync_sfx>%?\t%0, %C1" "ldrex<sync_sfx>%?\t%0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_load_acquire_exclusive<mode>" (define_insn "arm_load_acquire_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
@ -371,7 +373,8 @@
VUNSPEC_LAX)))] VUNSPEC_LAX)))]
"TARGET_HAVE_LDACQ" "TARGET_HAVE_LDACQ"
"ldaex<sync_sfx>%?\\t%0, %C1" "ldaex<sync_sfx>%?\\t%0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_load_exclusivesi" (define_insn "arm_load_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
@ -380,7 +383,8 @@
VUNSPEC_LL))] VUNSPEC_LL))]
"TARGET_HAVE_LDREX" "TARGET_HAVE_LDREX"
"ldrex%?\t%0, %C1" "ldrex%?\t%0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_load_acquire_exclusivesi" (define_insn "arm_load_acquire_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r") [(set (match_operand:SI 0 "s_register_operand" "=r")
@ -389,7 +393,8 @@
VUNSPEC_LAX))] VUNSPEC_LAX))]
"TARGET_HAVE_LDACQ" "TARGET_HAVE_LDACQ"
"ldaex%?\t%0, %C1" "ldaex%?\t%0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_load_exclusivedi" (define_insn "arm_load_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r") [(set (match_operand:DI 0 "s_register_operand" "=r")
@ -398,7 +403,8 @@
VUNSPEC_LL))] VUNSPEC_LL))]
"TARGET_HAVE_LDREXD" "TARGET_HAVE_LDREXD"
"ldrexd%?\t%0, %H0, %C1" "ldrexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_load_acquire_exclusivedi" (define_insn "arm_load_acquire_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r") [(set (match_operand:DI 0 "s_register_operand" "=r")
@ -407,7 +413,8 @@
VUNSPEC_LAX))] VUNSPEC_LAX))]
"TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
"ldaexd%?\t%0, %H0, %C1" "ldaexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_store_exclusive<mode>" (define_insn "arm_store_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r") [(set (match_operand:SI 0 "s_register_operand" "=&r")
@ -431,7 +438,8 @@
} }
return "strex<sync_sfx>%?\t%0, %2, %C1"; return "strex<sync_sfx>%?\t%0, %2, %C1";
} }
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_store_release_exclusivedi" (define_insn "arm_store_release_exclusivedi"
[(set (match_operand:SI 0 "s_register_operand" "=&r") [(set (match_operand:SI 0 "s_register_operand" "=&r")
@ -448,7 +456,8 @@
operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
return "stlexd%?\t%0, %2, %3, %C1"; return "stlexd%?\t%0, %2, %3, %C1";
} }
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "arm_store_release_exclusive<mode>" (define_insn "arm_store_release_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r") [(set (match_operand:SI 0 "s_register_operand" "=&r")
@ -459,4 +468,5 @@
VUNSPEC_SLX))] VUNSPEC_SLX))]
"TARGET_HAVE_LDACQ" "TARGET_HAVE_LDACQ"
"stlex<sync_sfx>%?\t%0, %2, %C1" "stlex<sync_sfx>%?\t%0, %2, %C1"
[(set_attr "predicable" "yes")]) [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])