aarch64.md: New movtf split.
* config/aarch64/aarch64.md: New movtf split. (*movtf_aarch64): Update. (aarch64_movdi_tilow): Handle TF modes and rename to aarch64_movdi_<mode>low. (aarch64_movdi_tihigh): Handle TF modes and rename to aarch64_movdi_<mode>high (aarch64_movtihigh_di): Handle TF modes and rename to aarch64_mov<mode>high_di (aarch64_movtilow_di): Handle TF modes and rename to aarch64_mov<mode>low_di (aarch64_movtilow_tilow): Remove spurious whitespace. * config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode splits. (aarch64_print_operand): Update. From-SVN: r198735
This commit is contained in:
Sofiane Naci
Sofiane Naci
parent
227eb34360
commit
12dc697479
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@ -1,3 +1,20 @@
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2013-05-09 Sofiane Naci <sofiane.naci@arm.com>
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* config/aarch64/aarch64.md: New movtf split.
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(*movtf_aarch64): Update.
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(aarch64_movdi_tilow): Handle TF modes and rename to
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aarch64_movdi_<mode>low.
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(aarch64_movdi_tihigh): Handle TF modes and rename to
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aarch64_movdi_<mode>high
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(aarch64_movtihigh_di): Handle TF modes and rename to
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aarch64_mov<mode>high_di
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(aarch64_movtilow_di): Handle TF modes and rename to
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aarch64_mov<mode>low_di
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(aarch64_movtilow_tilow): Remove spurious whitespace.
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* config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode
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splits.
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(aarch64_print_operand): Update.
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2013-05-09 Alan Modra <amodra@gmail.com>
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* configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and
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@ -604,49 +604,85 @@ aarch64_split_128bit_move (rtx dst, rtx src)
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{
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rtx low_dst;
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gcc_assert (GET_MODE (dst) == TImode);
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enum machine_mode src_mode = GET_MODE (src);
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enum machine_mode dst_mode = GET_MODE (dst);
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int src_regno = REGNO (src);
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int dst_regno = REGNO (dst);
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gcc_assert (dst_mode == TImode || dst_mode == TFmode);
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if (REG_P (dst) && REG_P (src))
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{
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int src_regno = REGNO (src);
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int dst_regno = REGNO (dst);
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gcc_assert (GET_MODE (src) == TImode);
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gcc_assert (src_mode == TImode || src_mode == TFmode);
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/* Handle r -> w, w -> r. */
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if (FP_REGNUM_P (dst_regno) && GP_REGNUM_P (src_regno))
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{
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emit_insn (gen_aarch64_movtilow_di (dst,
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gen_lowpart (word_mode, src)));
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emit_insn (gen_aarch64_movtihigh_di (dst,
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gen_highpart (word_mode, src)));
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return;
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switch (src_mode) {
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case TImode:
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emit_insn
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(gen_aarch64_movtilow_di (dst, gen_lowpart (word_mode, src)));
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emit_insn
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(gen_aarch64_movtihigh_di (dst, gen_highpart (word_mode, src)));
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return;
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case TFmode:
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emit_insn
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(gen_aarch64_movtflow_di (dst, gen_lowpart (word_mode, src)));
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emit_insn
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(gen_aarch64_movtfhigh_di (dst, gen_highpart (word_mode, src)));
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return;
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default:
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gcc_unreachable ();
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}
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}
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else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno))
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{
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emit_insn (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst),
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src));
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emit_insn (gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst),
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src));
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return;
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switch (src_mode) {
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case TImode:
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emit_insn
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(gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), src));
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emit_insn
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(gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), src));
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return;
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case TFmode:
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emit_insn
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(gen_aarch64_movdi_tflow (gen_lowpart (word_mode, dst), src));
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emit_insn
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(gen_aarch64_movdi_tfhigh (gen_highpart (word_mode, dst), src));
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return;
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default:
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gcc_unreachable ();
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}
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}
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/* Fall through to r -> r cases. */
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}
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low_dst = gen_lowpart (word_mode, dst);
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if (REG_P (low_dst)
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&& reg_overlap_mentioned_p (low_dst, src))
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{
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aarch64_emit_move (gen_highpart (word_mode, dst),
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gen_highpart_mode (word_mode, TImode, src));
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aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
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}
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else
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{
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aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
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aarch64_emit_move (gen_highpart (word_mode, dst),
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gen_highpart_mode (word_mode, TImode, src));
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}
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switch (dst_mode) {
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case TImode:
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low_dst = gen_lowpart (word_mode, dst);
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if (REG_P (low_dst)
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&& reg_overlap_mentioned_p (low_dst, src))
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{
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aarch64_emit_move (gen_highpart (word_mode, dst),
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gen_highpart_mode (word_mode, TImode, src));
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aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
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}
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else
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{
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aarch64_emit_move (low_dst, gen_lowpart (word_mode, src));
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aarch64_emit_move (gen_highpart (word_mode, dst),
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gen_highpart_mode (word_mode, TImode, src));
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}
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return;
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case TFmode:
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emit_move_insn (gen_rtx_REG (DFmode, dst_regno),
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gen_rtx_REG (DFmode, src_regno));
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emit_move_insn (gen_rtx_REG (DFmode, dst_regno + 1),
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gen_rtx_REG (DFmode, src_regno + 1));
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return;
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default:
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gcc_unreachable ();
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}
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}
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bool
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@ -3324,26 +3360,6 @@ aarch64_print_operand (FILE *f, rtx x, char code)
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asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]);
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break;
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case 'Q':
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/* Print the least significant register of a pair (TImode) of regs. */
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if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1))
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{
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output_operand_lossage ("invalid operand for '%%%c'", code);
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return;
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}
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asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)]);
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break;
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case 'R':
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/* Print the most significant register of a pair (TImode) of regs. */
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if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1))
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{
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output_operand_lossage ("invalid operand for '%%%c'", code);
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return;
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}
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asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)]);
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break;
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case 'm':
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/* Print a condition (eq, ne, etc). */
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@ -997,9 +997,9 @@
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|| register_operand (operands[1], TFmode))"
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"@
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orr\\t%0.16b, %1.16b, %1.16b
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mov\\t%0, %1\;mov\\t%H0, %H1
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fmov\\t%d0, %Q1\;fmov\\t%0.d[1], %R1
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fmov\\t%Q0, %d1\;fmov\\t%R0, %1.d[1]
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#
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#
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#
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movi\\t%0.2d, #0
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fmov\\t%s0, wzr
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ldr\\t%q0, %1
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@ -1013,6 +1013,17 @@
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(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")]
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)
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(define_split
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[(set (match_operand:TF 0 "register_operand" "")
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(match_operand:TF 1 "aarch64_reg_or_imm" ""))]
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"reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
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[(const_int 0)]
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{
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aarch64_split_128bit_move (operands[0], operands[1]);
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DONE;
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}
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)
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;; Operands 1 and 3 are tied together by the final condition; so we allow
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;; fairly lax checking on the second memory operation.
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(define_insn "load_pair<mode>"
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@ -3550,9 +3561,9 @@
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;; after or during reload as we don't want these patterns to start
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;; kicking in during the combiner.
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(define_insn "aarch64_movdi_tilow"
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(define_insn "aarch64_movdi_<mode>low"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(truncate:DI (match_operand:TI 1 "register_operand" "w")))]
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(truncate:DI (match_operand:TX 1 "register_operand" "w")))]
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"reload_completed || reload_in_progress"
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"fmov\\t%x0, %d1"
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[(set_attr "v8type" "fmovf2i")
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(set_attr "length" "4")
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])
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(define_insn "aarch64_movdi_tihigh"
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(define_insn "aarch64_movdi_<mode>high"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(truncate:DI
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(lshiftrt:TI (match_operand:TI 1 "register_operand" "w")
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(lshiftrt:TX (match_operand:TX 1 "register_operand" "w")
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(const_int 64))))]
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"reload_completed || reload_in_progress"
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"fmov\\t%x0, %1.d[1]"
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(set_attr "length" "4")
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])
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(define_insn "aarch64_movtihigh_di"
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[(set (zero_extract:TI (match_operand:TI 0 "register_operand" "+w")
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(define_insn "aarch64_mov<mode>high_di"
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[(set (zero_extract:TX (match_operand:TX 0 "register_operand" "+w")
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(const_int 64) (const_int 64))
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(zero_extend:TI (match_operand:DI 1 "register_operand" "r")))]
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(zero_extend:TX (match_operand:DI 1 "register_operand" "r")))]
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"reload_completed || reload_in_progress"
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"fmov\\t%0.d[1], %x1"
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[(set_attr "v8type" "fmovi2f")
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(set_attr "mode" "DI")
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(set_attr "length" "4")
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])
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(define_insn "aarch64_movtilow_di"
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[(set (match_operand:TI 0 "register_operand" "=w")
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(zero_extend:TI (match_operand:DI 1 "register_operand" "r")))]
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(define_insn "aarch64_mov<mode>low_di"
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[(set (match_operand:TX 0 "register_operand" "=w")
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(zero_extend:TX (match_operand:DI 1 "register_operand" "r")))]
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"reload_completed || reload_in_progress"
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"fmov\\t%d0, %x1"
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[(set_attr "v8type" "fmovi2f")
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(set_attr "mode" "DI")
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(set_attr "length" "4")
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@ -3601,7 +3610,6 @@
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(truncate:DI (match_operand:TI 1 "register_operand" "w"))))]
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"reload_completed || reload_in_progress"
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"fmov\\t%d0, %d1"
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[(set_attr "v8type" "fmovi2f")
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(set_attr "mode" "DI")
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(set_attr "length" "4")
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