From 13299a8e759c2c165f46cf661ef1b40e91cd831e Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 18 Oct 2012 23:46:52 +0200 Subject: [PATCH] i386.md (rdpmc): Remove expander. * config/i386/i386.md (rdpmc): Remove expander. (rdtsc): Ditto. (rdtscp): Ditto. (rdpmc): Rename from *rdpmc. (rdpmc_rex64): Rename from *rdpmc_rex64. (rdtsc): Rename from *rdtsc. (rdtsc_rex64): Rename from *rdtsc_rex64. (rdtscp): Rename from *rdtscp. (rdtscp_rex64): Rename from *rdtscp_rex64. * config/i386/i386.c (struct builtin_description bdesc_special_args) : Use CODE_FOR_NOTHING. : Ditto. (struct builtin_description bdesc__args) : Ditto. (ix86_expand_builtin) : Handle here. From-SVN: r192589 --- gcc/ChangeLog | 71 +++++++++++++----------- gcc/config/i386/i386.c | 67 +++++++++++++++++++++-- gcc/config/i386/i386.md | 118 +++------------------------------------- 3 files changed, 110 insertions(+), 146 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe7e76158f7..86c3f2fff0c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2012-10-18 Uros Bizjak + + * config/i386/i386.md (rdpmc): Remove expander. + (rdtsc): Ditto. + (rdtscp): Ditto. + (rdpmc): Rename from *rdpmc. + (rdpmc_rex64): Rename from *rdpmc_rex64. + (rdtsc): Rename from *rdtsc. + (rdtsc_rex64): Rename from *rdtsc_rex64. + (rdtscp): Rename from *rdtscp. + (rdtscp_rex64): Rename from *rdtscp_rex64. + + * config/i386/i386.c (struct builtin_description bdesc_special_args) + : Use CODE_FOR_NOTHING. + : Ditto. + (struct builtin_description bdesc__args) : Ditto. + (ix86_expand_builtin) : Handle here. + 2012-10-18 Jan-Benedict Glaw * config/sh/sh.c: Fix comment to silence warning. @@ -20,8 +38,7 @@ (altivec_vsumsws_nomode): Delete. (reduc_splus_, reduc_uplus_): Call gen_altivec_vsumsws instead of gen_altivec_vsumsws_nomode. - (altivec_lvlx, altivec_lvlxl, altivec_lvrx, altivec_lvrxl): - Add mode. + (altivec_lvlx, altivec_lvlxl, altivec_lvrx, altivec_lvrxl): Add mode. * config/rs6000/rs6000.md (probe_stack): Rename to... (probe_stack_): ... this. Add mode. Change pattern to use std instead of stw when appropriate. @@ -47,8 +64,7 @@ 2012-10-18 Matthew Gretton-Dann Ramana Radhakrishnan - * config/arm/arm.c (neon_builtin_data): Add vfma and vfms - builtins. + * config/arm/arm.c (neon_builtin_data): Add vfma and vfms builtins. * config/arm/neon-docgen.ml (intrinsic_groups): Add fused-multiply-* groups. * config/neon-gen.ml (print_feature_test_start): New function. @@ -120,15 +136,13 @@ * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to replace target_flags that gives us 63 possible switches. (x_rs6000_isa_flags): Save area for rs6000_isa_flags. - (x_rs6000_isa_flags_explicit): Save area for - rs6000_isa_flags_explicit. + (x_rs6000_isa_flags_explicit): Save area for rs6000_isa_flags_explicit. (rs6000_target_flags_explicit): Delete in favor of x_rs6000_isa_flags_explicit. (-mpowerpc64): Change all switches that used to be in target_flags to now be in rs6000_isa_flags. In using rs6000_isa_flags, the options machinary will generate names of the form OPITON_ - instead of TARGET_ and OPTION_MASK_ instead of - MASK_. + instead of TARGET_ and OPTION_MASK_ instead of MASK_. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. @@ -205,8 +219,7 @@ (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_can_inline_p): Likewise. - * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): - Likewise. + * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): Likewise. @@ -251,32 +264,23 @@ global_options_set structure. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): - Change use of target_flags to rs6000_isa_flags, - target_flags_explicit to rs6000_isa_flags_explicit, and MASK_ - to OPTION_MASK_. - * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): - Likewise. - * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): - Likewise. - * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): - Likewise. - * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): - Likewise. - * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): - Likewise. + Change use of target_flags to rs6000_isa_flags, target_flags_explicit + to rs6000_isa_flags_explicit, and MASK_ to OPTION_MASK_. + * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. + * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. - * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): - Likewise. - * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): - Likewise. + * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. + * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. - * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): - Likewise. + * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. @@ -298,7 +302,8 @@ 2012-10-17 Jan Hubicka * tree-ssa-loop-ivcanon.c (tree_estimate_loop_size): Add edge_to_cancel - parameter and use it to estimate code optimized out in the final iteration. + parameter and use it to estimate code optimized out in the final + iteration. (loop_edge_to_cancel): New function. (try_unroll_loop_completely): New IRRED_IVALIDATED parameter; handle unrolling loops with bounds given via max_loop_iteratins; @@ -643,8 +648,8 @@ * config/sh/iterators.md (QIHISIDI): New mode iterator. * config/sh/predicates.md (gbr_address_mem): New predicate. * config/sh/sh.md (*movdi_gbr_load, *movdi_gbr_store): New - insn_and_split. - Use QIHISIDI instead of QIHISI in unnamed GBR addressing splits. + insn_and_split. Use QIHISIDI instead of QIHISI in unnamed GBR + addressing splits. 2012-10-15 Oleg Endo @@ -659,7 +664,7 @@ * config.gcc: Match arm*-*-linux-* for ARM Linux/GNU. * doc/install.texi: Use arm-*-*linux-* instead of arm-*-*linux-gnueabi. -2012-10-13 Uros Bizjak +2012-10-15 Uros Bizjak * config/i386/sse.md (UNSPEC_MOVU): Remove. (UNSPEC_LOADU): New. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c345c20cd9e..e095d987296 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -26768,8 +26768,8 @@ static const struct builtin_description bdesc_pcmpistr[] = /* Special builtins with variable number of arguments. */ static const struct builtin_description bdesc_special_args[] = { - { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID }, - { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED }, + { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID }, + { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED }, { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID }, /* MMX */ @@ -26887,7 +26887,7 @@ static const struct builtin_description bdesc_args[] = { { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT }, { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 }, - { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT }, + { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT }, { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT }, { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT }, { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT }, @@ -30452,7 +30452,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, enum insn_code icode; tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); tree arg0, arg1, arg2, arg3, arg4; - rtx op0, op1, op2, op3, op4, pat; + rtx op0, op1, op2, op3, op4, pat, insn; enum machine_mode mode0, mode1, mode2, mode3, mode4; unsigned int fcode = DECL_FUNCTION_CODE (fndecl); @@ -30633,6 +30633,65 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return target; } + case IX86_BUILTIN_RDPMC: + case IX86_BUILTIN_RDTSC: + case IX86_BUILTIN_RDTSCP: + + op0 = gen_reg_rtx (DImode); + op1 = gen_reg_rtx (DImode); + + if (fcode == IX86_BUILTIN_RDPMC) + { + arg0 = CALL_EXPR_ARG (exp, 0); + op2 = expand_normal (arg0); + if (!register_operand (op2, SImode)) + op2 = copy_to_mode_reg (SImode, op2); + + insn = (TARGET_64BIT + ? gen_rdpmc_rex64 (op0, op1, op2) + : gen_rdpmc (op0, op2)); + emit_insn (insn); + } + else if (fcode == IX86_BUILTIN_RDTSC) + { + insn = (TARGET_64BIT + ? gen_rdtsc_rex64 (op0, op1) + : gen_rdtsc (op0)); + emit_insn (insn); + } + else + { + op2 = gen_reg_rtx (SImode); + + insn = (TARGET_64BIT + ? gen_rdtscp_rex64 (op0, op1, op2) + : gen_rdtscp (op0, op2)); + emit_insn (insn); + + arg0 = CALL_EXPR_ARG (exp, 0); + op4 = expand_normal (arg0); + if (!address_operand (op4, VOIDmode)) + { + op4 = convert_memory_address (Pmode, op4); + op4 = copy_addr_to_reg (op4); + } + emit_move_insn (gen_rtx_MEM (SImode, op4), op2); + } + + if (target == 0) + target = gen_reg_rtx (mode); + + if (TARGET_64BIT) + { + op1 = expand_simple_binop (DImode, ASHIFT, op1, GEN_INT (32), + op1, 1, OPTAB_DIRECT); + op0 = expand_simple_binop (DImode, IOR, op0, op1, + op0, 1, OPTAB_DIRECT); + } + + emit_move_insn (target, op0); + return target; + case IX86_BUILTIN_LLWPCB: arg0 = CALL_EXPR_ARG (exp, 0); op0 = expand_normal (arg0); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index fa10cb4a427..299115d4ac4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -17975,40 +17975,7 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "DI")]) -(define_expand "rdpmc" - [(match_operand:DI 0 "register_operand") - (match_operand:SI 1 "register_operand")] - "" -{ - rtx reg = gen_reg_rtx (DImode); - rtx si; - - si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, operands[1]), - UNSPECV_RDPMC); - - if (TARGET_64BIT) - { - rtvec vec = rtvec_alloc (2); - rtx load = gen_rtx_PARALLEL (VOIDmode, vec); - rtx upper = gen_reg_rtx (DImode); - rtx di = gen_rtx_UNSPEC_VOLATILE (DImode, - gen_rtvec (1, const0_rtx), - UNSPECV_RDPMC); - RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, si); - RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di); - emit_insn (load); - upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32), - NULL, 1, OPTAB_DIRECT); - reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1, - OPTAB_DIRECT); - } - else - emit_insn (gen_rtx_SET (VOIDmode, reg, si)); - emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg)); - DONE; -}) - -(define_insn "*rdpmc" +(define_insn "rdpmc" [(set (match_operand:DI 0 "register_operand" "=A") (unspec_volatile:DI [(match_operand:SI 1 "register_operand" "c")] UNSPECV_RDPMC))] @@ -18017,44 +17984,18 @@ [(set_attr "type" "other") (set_attr "length" "2")]) -(define_insn "*rdpmc_rex64" +(define_insn "rdpmc_rex64" [(set (match_operand:DI 0 "register_operand" "=a") (unspec_volatile:DI [(match_operand:SI 2 "register_operand" "c")] UNSPECV_RDPMC)) - (set (match_operand:DI 1 "register_operand" "=d") - (unspec_volatile:DI [(const_int 0)] UNSPECV_RDPMC))] + (set (match_operand:DI 1 "register_operand" "=d") + (unspec_volatile:DI [(match_dup 2)] UNSPECV_RDPMC))] "TARGET_64BIT" "rdpmc" [(set_attr "type" "other") (set_attr "length" "2")]) -(define_expand "rdtsc" - [(set (match_operand:DI 0 "register_operand") - (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))] - "" -{ - if (TARGET_64BIT) - { - rtvec vec = rtvec_alloc (2); - rtx load = gen_rtx_PARALLEL (VOIDmode, vec); - rtx upper = gen_reg_rtx (DImode); - rtx lower = gen_reg_rtx (DImode); - rtx src = gen_rtx_UNSPEC_VOLATILE (DImode, - gen_rtvec (1, const0_rtx), - UNSPECV_RDTSC); - RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, lower, src); - RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, src); - emit_insn (load); - upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32), - NULL, 1, OPTAB_DIRECT); - lower = expand_simple_binop (DImode, IOR, lower, upper, lower, 1, - OPTAB_DIRECT); - emit_insn (gen_rtx_SET (VOIDmode, operands[0], lower)); - DONE; - } -}) - -(define_insn "*rdtsc" +(define_insn "rdtsc" [(set (match_operand:DI 0 "register_operand" "=A") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))] "!TARGET_64BIT" @@ -18062,7 +18003,7 @@ [(set_attr "type" "other") (set_attr "length" "2")]) -(define_insn "*rdtsc_rex64" +(define_insn "rdtsc_rex64" [(set (match_operand:DI 0 "register_operand" "=a") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC)) (set (match_operand:DI 1 "register_operand" "=d") @@ -18072,48 +18013,7 @@ [(set_attr "type" "other") (set_attr "length" "2")]) -(define_expand "rdtscp" - [(match_operand:DI 0 "register_operand") - (match_operand:SI 1 "memory_operand")] - "" -{ - rtx di = gen_rtx_UNSPEC_VOLATILE (DImode, - gen_rtvec (1, const0_rtx), - UNSPECV_RDTSCP); - rtx si = gen_rtx_UNSPEC_VOLATILE (SImode, - gen_rtvec (1, const0_rtx), - UNSPECV_RDTSCP); - rtx reg = gen_reg_rtx (DImode); - rtx tmp = gen_reg_rtx (SImode); - - if (TARGET_64BIT) - { - rtvec vec = rtvec_alloc (3); - rtx load = gen_rtx_PARALLEL (VOIDmode, vec); - rtx upper = gen_reg_rtx (DImode); - RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di); - RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di); - RTVEC_ELT (vec, 2) = gen_rtx_SET (VOIDmode, tmp, si); - emit_insn (load); - upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32), - NULL, 1, OPTAB_DIRECT); - reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1, - OPTAB_DIRECT); - } - else - { - rtvec vec = rtvec_alloc (2); - rtx load = gen_rtx_PARALLEL (VOIDmode, vec); - RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di); - RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, tmp, si); - emit_insn (load); - } - emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg)); - emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp)); - DONE; -}) - -(define_insn "*rdtscp" +(define_insn "rdtscp" [(set (match_operand:DI 0 "register_operand" "=A") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP)) (set (match_operand:SI 1 "register_operand" "=c") @@ -18123,11 +18023,11 @@ [(set_attr "type" "other") (set_attr "length" "3")]) -(define_insn "*rdtscp_rex64" +(define_insn "rdtscp_rex64" [(set (match_operand:DI 0 "register_operand" "=a") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP)) (set (match_operand:DI 1 "register_operand" "=d") - (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP)) + (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP)) (set (match_operand:SI 2 "register_operand" "=c") (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))] "TARGET_64BIT"