i386.md (*ashl<mode>3_mask): Rewrite as define_insn.
2013-04-01 Wei Mi <wmi@google.com> * config/i386/i386.md (*ashl<mode>3_mask): Rewrite as define_insn. Truncate operand 2 using %b asm operand modifier. (*<shift_insn><mode>3_mask): Ditto. (*<rotate_insn><mode>3_mask): Ditto. From-SVN: r197308
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2013-04-01 Wei Mi <wmi@google.com>
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* config/i386/i386.md (*ashl<mode>3_mask): Rewrite as define_insn.
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Truncate operand 2 using %b asm operand modifier.
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(*<shift_insn><mode>3_mask): Ditto.
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(*<rotate_insn><mode>3_mask): Ditto.
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2013-04-01 Steven Bosscher <steven@gcc.gnu.org>
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2013-04-01 Steven Bosscher <steven@gcc.gnu.org>
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PR middle-end/56798
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PR middle-end/56798
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@ -8647,28 +8647,20 @@
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})
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})
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;; Avoid useless masking of count operand.
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;; Avoid useless masking of count operand.
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(define_insn_and_split "*ashl<mode>3_mask"
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(define_insn "*ashl<mode>3_mask"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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(ashift:SWI48
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(ashift:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(subreg:QI
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(subreg:QI
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(and:SI
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(and:SI
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(match_operand:SI 2 "nonimmediate_operand" "c")
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(match_operand:SI 2 "register_operand" "c")
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
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"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(ashift:SWI48 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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{
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if (can_create_pseudo_p ())
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return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
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operands [2] = force_reg (SImode, operands[2]);
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operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
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}
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}
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[(set_attr "type" "ishift")
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[(set_attr "type" "ishift")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")])
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@ -9157,28 +9149,20 @@
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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;; Avoid useless masking of count operand.
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;; Avoid useless masking of count operand.
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(define_insn_and_split "*<shift_insn><mode>3_mask"
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(define_insn "*<shift_insn><mode>3_mask"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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(any_shiftrt:SWI48
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(any_shiftrt:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(subreg:QI
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(subreg:QI
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(and:SI
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(and:SI
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(match_operand:SI 2 "nonimmediate_operand" "c")
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(match_operand:SI 2 "register_operand" "c")
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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{
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if (can_create_pseudo_p ())
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return "<shift>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
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operands [2] = force_reg (SImode, operands[2]);
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operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
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}
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}
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[(set_attr "type" "ishift")
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[(set_attr "type" "ishift")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")])
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@ -9620,28 +9604,20 @@
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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;; Avoid useless masking of count operand.
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;; Avoid useless masking of count operand.
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(define_insn_and_split "*<rotate_insn><mode>3_mask"
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(define_insn "*<rotate_insn><mode>3_mask"
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
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(any_rotate:SWI48
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(any_rotate:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(match_operand:SWI48 1 "nonimmediate_operand" "0")
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(subreg:QI
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(subreg:QI
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(and:SI
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(and:SI
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(match_operand:SI 2 "nonimmediate_operand" "c")
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(match_operand:SI 2 "register_operand" "c")
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(match_operand:SI 3 "const_int_operand" "n")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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== GET_MODE_BITSIZE (<MODE>mode)-1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(any_rotate:SWI48 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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{
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if (can_create_pseudo_p ())
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return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
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operands [2] = force_reg (SImode, operands[2]);
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operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
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}
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}
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[(set_attr "type" "rotate")
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[(set_attr "type" "rotate")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")])
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