rs6000: Merge rotlsi3 and rotldi3
This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl mnemonics, because they are shorter and more importantly they look the same for 32-bit and 64-bit. From-SVN: r211878
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137b8eb295
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@ -1,3 +1,12 @@
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2014-06-22 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (rotlsi3, *rotlsi3_internal2 and split,
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*rotlsi3_internal3 and split, rotldi3, *rotldi3_internal2 and split,
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*rotldi3_internal3 and split): Delete, merge into...
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(rotl<mode>3, rotl<mode>3_dot, rotl<mode>3_dot2): New.
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(*rotlsi3_64): Fix formatting. Fix condition. Replace "i" by "n".
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Use "rotlw" extended mnemonic.
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2014-06-22 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (ashlsi3, two anonymous define_insns
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@ -3859,92 +3859,82 @@
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")])
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(define_insn "rotlsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
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(define_insn "rotl<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
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""
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"@
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rlwnm %0,%1,%2,0xffffffff
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rlwinm %0,%1,%h2,0xffffffff"
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rotl<wd> %0,%1,%2
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rotl<wd>i %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_64"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(zero_extend:DI
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(zero_extend:DI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
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"TARGET_64BIT"
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(match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
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"TARGET_POWERPC64"
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"@
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rlwnm %0,%1,%2,0xffffffff
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rlwinm %0,%1,%h2,0xffffffff"
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rotlw %0,%1,%2
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rotlwi %0,%1,%h2"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r"))]
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""
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"@
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rlwnm. %3,%1,%2,0xffffffff
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rlwinm. %3,%1,%h2,0xffffffff
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"reload_completed"
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[(set (match_dup 3)
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(rotate:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn "*rotlsi3_internal3"
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(define_insn_and_split "*rotl<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(rotate:SI (match_dup 1) (match_dup 2)))]
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""
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(clobber (match_scratch:GPR 0 "=r,r,r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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rlwnm. %0,%1,%2,0xffffffff
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rlwinm. %0,%1,%h2,0xffffffff
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rotl<wd>. %0,%1,%2
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rotl<wd>i. %0,%1,%<hH>2
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(rotate:SI (match_dup 1) (match_dup 2)))]
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"reload_completed"
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"&& reload_completed"
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[(set (match_dup 0)
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(rotate:SI (match_dup 1) (match_dup 2)))
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(rotate:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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""
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_insn_and_split "*rotl<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
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(rotate:GPR (match_dup 1)
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(match_dup 2)))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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rotl<wd>. %0,%1,%2
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rotl<wd>i. %0,%1,%<hH>2
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#
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#"
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"&& reload_completed"
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[(set (match_dup 0)
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(rotate:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_insn "*rotlsi3_internal4"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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@ -6962,81 +6952,6 @@
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DONE;
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})
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(define_insn "rotldi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
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"TARGET_POWERPC64"
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"@
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rldcl %0,%1,%2,0
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rldicl %0,%1,%H2,0"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotldi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(clobber (match_scratch:DI 3 "=r,r,r,r"))]
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"TARGET_64BIT"
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"@
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rldcl. %3,%1,%2,0
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rldicl. %3,%1,%H2,0
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:DI 3 ""))]
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"TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 3)
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(rotate:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn "*rotldi3_internal3"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
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(rotate:DI (match_dup 1) (match_dup 2)))]
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"TARGET_64BIT"
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"@
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rldcl. %0,%1,%2,0
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rldicl. %0,%1,%H2,0
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "")
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(rotate:DI (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 0)
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(rotate:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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(define_insn "*rotldi3_internal4"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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