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aarch64: Update flags for bfloat16 builtins

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This patch updates the flags for the bfloat16 builtins.
The bfdot ones aren't affected by the FPCR/FPSR so can be AUTO_FP
whereas the bfmlal ones follow the normal floating-point instructions and get FP.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def (bfdot_lane, bfdot_laneq): Use
	AUTO_FP flags.
	(bfmlalb_lane, bfmlalt_lane, bfmlalb_lane_q, bfmlalt_lane_q): Use FP flags.
This commit is contained in:
Kyrylo Tkachov 2021-02-01 23:03:49 +00:00
parent 4b8a7a6e81
commit 13d8be9121
1 changed files with 6 additions and 6 deletions
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12
gcc/config/aarch64/aarch64-simd-builtins.def
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@ -816,8 +816,8 @@
/* Implemented by aarch64_bfdot{_lane}{q}<mode>. */
VAR2 (TERNOP, bfdot, 0, AUTO_FP, v2sf, v4sf)
VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, ALL, v2sf, v4sf)
VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, ALL, v2sf, v4sf)
VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, AUTO_FP, v2sf, v4sf)
VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, AUTO_FP, v2sf, v4sf)
/* Implemented by aarch64_bfmmlaqv4sf */
VAR1 (TERNOP, bfmmlaq, 0, AUTO_FP, v4sf)
@ -825,10 +825,10 @@
/* Implemented by aarch64_bfmlal<bt>{_lane{q}}v4sf */
VAR1 (TERNOP, bfmlalb, 0, FP, v4sf)
VAR1 (TERNOP, bfmlalt, 0, FP, v4sf)
VAR1 (QUADOP_LANE, bfmlalb_lane, 0, ALL, v4sf)
VAR1 (QUADOP_LANE, bfmlalt_lane, 0, ALL, v4sf)
VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, ALL, v4sf)
VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, ALL, v4sf)
VAR1 (QUADOP_LANE, bfmlalb_lane, 0, FP, v4sf)
VAR1 (QUADOP_LANE, bfmlalt_lane, 0, FP, v4sf)
VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, FP, v4sf)
VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, FP, v4sf)
/* Implemented by aarch64_vget_lo/hi_halfv8bf. */
VAR1 (UNOP, vget_lo_half, 0, AUTO_FP, v8bf)