alpha.md (@unaligned_store<mode>): Rename from unaligned_store<mode>.
* config/alpha/alpha.md (@unaligned_store<mode>): Rename from unaligned_store<mode>. (@reload_in<mode>_aligned): Rename from reload_in<mode>_aligned. * config/alpha/sync.md (@load_locked_<mode>): Rename from load_locked_<mode>. (@store_conditional_<mode>): Rename from store_conditional_<mode>. (@atomic_compare_and_swap<mode>_1): Rename from atomic_compare_and_swap<mode>_1. (@atomic_exchange<mode>_1): Rename from atomic_exchange<mode>_1. * config/alpha/alpha.c (alpha_expand_mov_nobwx): Use gen_reload_in_aligned and gen_unaligned_store. (emit_load_locked): Remove. (emit_store_conditional): Ditto. (alpha_split_atomic_op): Use gen_load_locked and gen_store_conditional. (alpha_split_compare_and_swap): Ditto. (alpha_expand_compare_and_swap_12): Use gen_atomic_compare_and_swap_1. (alpha_split_compare_and_swap_12): Use gen_load_locked and gen_store_conditional. (alpha_split_atomic_exchange): Ditto. (alpha_expand_atomic_exchange_12): Use gen_atomic_exchange_1. (alpha_split_atomic_exchange_12): Use gen_load_locked and gen_store_conditional. From-SVN: r272523
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
6bd4871707
commit
145f748f0c
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@ -1,3 +1,28 @@
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2019-06-20 Uroš Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (@unaligned_store<mode>):
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Rename from unaligned_store<mode>.
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(@reload_in<mode>_aligned): Rename from reload_in<mode>_aligned.
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* config/alpha/sync.md (@load_locked_<mode>): Rename
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from load_locked_<mode>.
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(@store_conditional_<mode>): Rename from store_conditional_<mode>.
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(@atomic_compare_and_swap<mode>_1): Rename
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from atomic_compare_and_swap<mode>_1.
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(@atomic_exchange<mode>_1): Rename from atomic_exchange<mode>_1.
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* config/alpha/alpha.c (alpha_expand_mov_nobwx):
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Use gen_reload_in_aligned and gen_unaligned_store.
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(emit_load_locked): Remove.
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(emit_store_conditional): Ditto.
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(alpha_split_atomic_op): Use gen_load_locked and gen_store_conditional.
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(alpha_split_compare_and_swap): Ditto.
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(alpha_expand_compare_and_swap_12): Use gen_atomic_compare_and_swap_1.
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(alpha_split_compare_and_swap_12): Use gen_load_locked
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and gen_store_conditional.
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(alpha_split_atomic_exchange): Ditto.
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(alpha_expand_atomic_exchange_12): Use gen_atomic_exchange_1.
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(alpha_split_atomic_exchange_12): Use gen_load_locked
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and gen_store_conditional.
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2019-06-20 Richard Earnshaw <rearnsha@arm.com>
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* config/aarch64/aarch64-errata.h: New file.
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@ -2292,10 +2292,7 @@ alpha_expand_mov_nobwx (machine_mode mode, rtx *operands)
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{
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if (reload_in_progress)
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{
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if (mode == QImode)
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seq = gen_reload_inqi_aligned (operands[0], operands[1]);
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else
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seq = gen_reload_inhi_aligned (operands[0], operands[1]);
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seq = gen_reload_in_aligned (mode, operands[0], operands[1]);
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emit_insn (seq);
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}
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else
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@ -2378,10 +2375,8 @@ alpha_expand_mov_nobwx (machine_mode mode, rtx *operands)
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rtx temp3 = gen_reg_rtx (DImode);
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rtx ua = get_unaligned_address (operands[0]);
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if (mode == QImode)
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seq = gen_unaligned_storeqi (ua, operands[1], temp1, temp2, temp3);
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else
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seq = gen_unaligned_storehi (ua, operands[1], temp1, temp2, temp3);
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seq = gen_unaligned_store
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(mode, ua, operands[1], temp1, temp2, temp3);
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alpha_set_memflags (seq, operands[0]);
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emit_insn (seq);
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@ -4349,34 +4344,6 @@ emit_unlikely_jump (rtx cond, rtx label)
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add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
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}
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/* A subroutine of the atomic operation splitters. Emit a load-locked
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instruction in MODE. */
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static void
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emit_load_locked (machine_mode mode, rtx reg, rtx mem)
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{
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rtx (*fn) (rtx, rtx) = NULL;
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if (mode == SImode)
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fn = gen_load_locked_si;
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else if (mode == DImode)
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fn = gen_load_locked_di;
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emit_insn (fn (reg, mem));
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}
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/* A subroutine of the atomic operation splitters. Emit a store-conditional
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instruction in MODE. */
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static void
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emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
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{
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rtx (*fn) (rtx, rtx, rtx) = NULL;
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if (mode == SImode)
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fn = gen_store_conditional_si;
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else if (mode == DImode)
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fn = gen_store_conditional_di;
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emit_insn (fn (res, mem, val));
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}
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/* Subroutines of the atomic operation splitters. Emit barriers
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as needed for the memory MODEL. */
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@ -4448,7 +4415,7 @@ alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val, rtx before,
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if (before == NULL)
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before = scratch;
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emit_load_locked (mode, before, mem);
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emit_insn (gen_load_locked (mode, before, mem));
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if (code == NOT)
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{
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@ -4463,7 +4430,7 @@ alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val, rtx before,
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emit_insn (gen_rtx_SET (after, copy_rtx (x)));
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emit_insn (gen_rtx_SET (scratch, x));
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emit_store_conditional (mode, cond, mem, scratch);
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emit_insn (gen_store_conditional (mode, cond, mem, scratch));
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x = gen_rtx_EQ (DImode, cond, const0_rtx);
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emit_unlikely_jump (x, label);
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@ -4502,7 +4469,7 @@ alpha_split_compare_and_swap (rtx operands[])
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}
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label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
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emit_load_locked (mode, retval, mem);
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emit_insn (gen_load_locked (mode, retval, mem));
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x = gen_lowpart (DImode, retval);
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if (oldval == const0_rtx)
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@ -4519,7 +4486,8 @@ alpha_split_compare_and_swap (rtx operands[])
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emit_unlikely_jump (x, label2);
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emit_move_insn (cond, newval);
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emit_store_conditional (mode, cond, mem, gen_lowpart (mode, cond));
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emit_insn (gen_store_conditional
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(mode, cond, mem, gen_lowpart (mode, cond)));
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if (!is_weak)
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{
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@ -4542,7 +4510,6 @@ alpha_expand_compare_and_swap_12 (rtx operands[])
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rtx cond, dst, mem, oldval, newval, is_weak, mod_s, mod_f;
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machine_mode mode;
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rtx addr, align, wdst;
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rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
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cond = operands[0];
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dst = operands[1];
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@ -4567,12 +4534,9 @@ alpha_expand_compare_and_swap_12 (rtx operands[])
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newval = emit_insxl (mode, newval, addr);
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wdst = gen_reg_rtx (DImode);
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if (mode == QImode)
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gen = gen_atomic_compare_and_swapqi_1;
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else
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gen = gen_atomic_compare_and_swaphi_1;
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emit_insn (gen (cond, wdst, mem, oldval, newval, align,
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is_weak, mod_s, mod_f));
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emit_insn (gen_atomic_compare_and_swap_1
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(mode, cond, wdst, mem, oldval, newval, align,
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is_weak, mod_s, mod_f));
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emit_move_insn (dst, gen_lowpart (mode, wdst));
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}
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@ -4614,7 +4578,7 @@ alpha_split_compare_and_swap_12 (rtx operands[])
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}
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label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
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emit_load_locked (DImode, scratch, mem);
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emit_insn (gen_load_locked (DImode, scratch, mem));
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width = GEN_INT (GET_MODE_BITSIZE (mode));
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mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
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@ -4638,7 +4602,7 @@ alpha_split_compare_and_swap_12 (rtx operands[])
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if (newval != const0_rtx)
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emit_insn (gen_iordi3 (cond, cond, newval));
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emit_store_conditional (DImode, cond, mem, cond);
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emit_insn (gen_store_conditional (DImode, cond, mem, cond));
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if (!is_weak)
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{
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@ -4678,9 +4642,9 @@ alpha_split_atomic_exchange (rtx operands[])
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label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
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emit_label (XEXP (label, 0));
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emit_load_locked (mode, retval, mem);
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emit_insn (gen_load_locked (mode, retval, mem));
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emit_move_insn (scratch, val);
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emit_store_conditional (mode, cond, mem, scratch);
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emit_insn (gen_store_conditional (mode, cond, mem, scratch));
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x = gen_rtx_EQ (DImode, cond, const0_rtx);
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emit_unlikely_jump (x, label);
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@ -4694,7 +4658,6 @@ alpha_expand_atomic_exchange_12 (rtx operands[])
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rtx dst, mem, val, model;
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machine_mode mode;
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rtx addr, align, wdst;
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rtx (*gen) (rtx, rtx, rtx, rtx, rtx);
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dst = operands[0];
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mem = operands[1];
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@ -4714,11 +4677,7 @@ alpha_expand_atomic_exchange_12 (rtx operands[])
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val = emit_insxl (mode, val, addr);
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wdst = gen_reg_rtx (DImode);
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if (mode == QImode)
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gen = gen_atomic_exchangeqi_1;
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else
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gen = gen_atomic_exchangehi_1;
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emit_insn (gen (wdst, mem, val, align, model));
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emit_insn (gen_atomic_exchange_1 (mode, wdst, mem, val, align, model));
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emit_move_insn (dst, gen_lowpart (mode, wdst));
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}
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@ -4750,7 +4709,7 @@ alpha_split_atomic_exchange_12 (rtx operands[])
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label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
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emit_label (XEXP (label, 0));
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emit_load_locked (DImode, scratch, mem);
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emit_insn (gen_load_locked (DImode, scratch, mem));
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width = GEN_INT (GET_MODE_BITSIZE (mode));
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mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
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@ -4759,7 +4718,7 @@ alpha_split_atomic_exchange_12 (rtx operands[])
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if (val != const0_rtx)
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emit_insn (gen_iordi3 (scratch, scratch, val));
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emit_store_conditional (DImode, scratch, mem, scratch);
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emit_insn (gen_store_conditional (DImode, scratch, mem, scratch));
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x = gen_rtx_EQ (DImode, scratch, const0_rtx);
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emit_unlikely_jump (x, label);
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@ -4232,7 +4232,7 @@
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;; be the same temporary, if desired. If the address is in a register,
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;; operand 2 can be that register.
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(define_expand "unaligned_store<mode>"
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(define_expand "@unaligned_store<mode>"
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[(set (match_operand:DI 3 "register_operand")
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(mem:DI (and:DI (match_operand:DI 0 "address_operand")
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(const_int -8))))
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@ -4417,7 +4417,7 @@
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;; always get a proper address for a stack slot during reload_foo
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;; expansion, so we must delay our address manipulations until after.
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(define_insn_and_split "reload_in<mode>_aligned"
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(define_insn_and_split "@reload_in<mode>_aligned"
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[(set (match_operand:I12MODE 0 "register_operand" "=r")
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(match_operand:I12MODE 1 "memory_operand" "m"))]
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"!TARGET_BWX && (reload_in_progress || reload_completed)"
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@ -43,7 +43,7 @@
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"mb"
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[(set_attr "type" "mb")])
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(define_insn "load_locked_<mode>"
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(define_insn "@load_locked_<mode>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(unspec_volatile:I48MODE
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[(match_operand:I48MODE 1 "memory_operand" "m")]
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@ -52,7 +52,7 @@
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"ld<modesuffix>_l %0,%1"
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[(set_attr "type" "ld_l")])
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(define_insn "store_conditional_<mode>"
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(define_insn "@store_conditional_<mode>"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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(set (match_operand:I48MODE 1 "memory_operand" "=m")
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@ -132,7 +132,7 @@
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DONE;
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})
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(define_insn_and_split "atomic_compare_and_swap<mode>_1"
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(define_insn_and_split "@atomic_compare_and_swap<mode>_1"
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[(set (match_operand:DI 0 "register_operand" "=&r") ;; bool out
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(unspec_volatile:DI [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_operand:DI 1 "register_operand" "=&r") ;; val out
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@ -189,7 +189,7 @@
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DONE;
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})
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(define_insn_and_split "atomic_exchange<mode>_1"
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(define_insn_and_split "@atomic_exchange<mode>_1"
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[(set (match_operand:DI 0 "register_operand" "=&r") ;; output
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(zero_extend:DI
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(match_operand:I12MODE 1 "mem_noofs_operand" "+w"))) ;; memory
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