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Add execution tests of ARM TRN Intrinsics.

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* gcc.target/arm/simd/vtrnqf32_1.c: New file.
	* gcc.target/arm/simd/vtrnqp16_1.c: New file.
	* gcc.target/arm/simd/vtrnqp8_1.c: New file.
	* gcc.target/arm/simd/vtrnqs16_1.c: New file.
	* gcc.target/arm/simd/vtrnqs32_1.c: New file.
	* gcc.target/arm/simd/vtrnqs8_1.c: New file.
	* gcc.target/arm/simd/vtrnqu16_1.c: New file.
	* gcc.target/arm/simd/vtrnqu32_1.c: New file.
	* gcc.target/arm/simd/vtrnqu8_1.c: New file.
	* gcc.target/arm/simd/vtrnf32_1.c: New file.
	* gcc.target/arm/simd/vtrnp16_1.c: New file.
	* gcc.target/arm/simd/vtrnp8_1.c: New file.
	* gcc.target/arm/simd/vtrns16_1.c: New file.
	* gcc.target/arm/simd/vtrns32_1.c: New file.
	* gcc.target/arm/simd/vtrns8_1.c: New file.
	* gcc.target/arm/simd/vtrnu16_1.c: New file.
	* gcc.target/arm/simd/vtrnu32_1.c: New file.
	* gcc.target/arm/simd/vtrnu8_1.c: New file.

From-SVN: r210422
This commit is contained in:
Alan Lawrence 2014-05-14 13:23:29 +00:00 committed by Alan Lawrence
parent 9cdea277ef
commit 14e2152213
19 changed files with 237 additions and 0 deletions
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21
gcc/testsuite/ChangeLog
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@ -1,3 +1,24 @@
2014-05-14 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vtrnqf32_1.c: New file.
* gcc.target/arm/simd/vtrnqp16_1.c: New file.
* gcc.target/arm/simd/vtrnqp8_1.c: New file.
* gcc.target/arm/simd/vtrnqs16_1.c: New file.
* gcc.target/arm/simd/vtrnqs32_1.c: New file.
* gcc.target/arm/simd/vtrnqs8_1.c: New file.
* gcc.target/arm/simd/vtrnqu16_1.c: New file.
* gcc.target/arm/simd/vtrnqu32_1.c: New file.
* gcc.target/arm/simd/vtrnqu8_1.c: New file.
* gcc.target/arm/simd/vtrnf32_1.c: New file.
* gcc.target/arm/simd/vtrnp16_1.c: New file.
* gcc.target/arm/simd/vtrnp8_1.c: New file.
* gcc.target/arm/simd/vtrns16_1.c: New file.
* gcc.target/arm/simd/vtrns32_1.c: New file.
* gcc.target/arm/simd/vtrns8_1.c: New file.
* gcc.target/arm/simd/vtrnu16_1.c: New file.
* gcc.target/arm/simd/vtrnu32_1.c: New file.
* gcc.target/arm/simd/vtrnu8_1.c: New file.
2014-05-14 Ilya Tocar <ilya.tocar@intel.com>
* gcc.target/i386/clflushopt-1.c: New.

12
gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c Normal file
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/* Test the `vtrnf32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnf32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c Normal file
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/* Test the `vtrnp16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnp16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnp8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnp8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c Normal file
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/* Test the `vtrnQf32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqf32.x"
/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c Normal file
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/* Test the `vtrnQp16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqp16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c Normal file
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/* Test the `vtrnQp8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqp8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c Normal file
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/* Test the `vtrnQs16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqs16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c Normal file
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/* Test the `vtrnQs32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqs32.x"
/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c Normal file
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/* Test the `vtrnQs8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqs8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnQu16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqu16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

12
gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c Normal file
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/* Test the `vtrnQu32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqu32.x"
/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnQu8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnqu8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrns16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrns16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrns32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrns32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrns8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrns8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnu16' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnu16.x"
/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnu32' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnu32.x"
/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c Normal file
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@ -0,0 +1,12 @@
/* Test the `vtrnu8' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O1 -fno-inline" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include "../../aarch64/simd/vtrnu8.x"
/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */