diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6e29e53a4f..43027e0c351 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-12-08  Andrew Pinski  <apinski@cavium.com>
+
+	* config/mips/mips-cpus.def (octeon+): New CPU.
+	* config/mips/mips-tables.opt: Regenerate.
+	* config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.
+
 2011-12-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
 	PR middle-end/39976
diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index 35fd5169167..39f46ab4bbe 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -145,3 +145,4 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
 
 /* MIPS64 Release 2 processors.  */
 MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
+MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
index 4e410f0f010..bd885261690 100644
--- a/gcc/config/mips/mips-tables.opt
+++ b/gcc/config/mips/mips-tables.opt
@@ -603,3 +603,6 @@ Enum(mips_arch_opt_value) String(loongson3a) Value(79) Canonical
 EnumValue
 Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical
 
+EnumValue
+Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical
+
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 236afbb4a34..ee40cfabc9a 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -329,7 +329,10 @@ struct mips_cpu_info {
 								\
       macro = concat ((PREFIX), "_", (INFO)->name, NULL);	\
       for (p = macro; *p != 0; p++)				\
-	*p = TOUPPER (*p);					\
+        if (*p == '+')                                          \
+          *p = 'P';                                             \
+        else                                                    \
+          *p = TOUPPER (*p);                                    \
 								\
       builtin_define (macro);					\
       builtin_define_with_value ((PREFIX), (INFO)->name, 1);	\
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9d4f286418e..8ad5ffec9c8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2011-12-08  Andrew Pinski  <apinski@cavium.com>
+
+	* cc.target/mips/mult-1.c: Forbid all Octeon processors.
+	* gcc.target/mips/dmult-1.c: Likewise.
+	* gcc.target/mips/branch-1.c: Likewise.
+	* gcc.target/mips/extend-1.c: Likewise.
+
 2011-12-08  Jason Merrill  <jason@redhat.com>
 
 	PR c++/51318
diff --git a/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc/testsuite/gcc.target/mips/branch-1.c
index 62d6bbb619a..2f4510f8dd6 100644
--- a/gcc/testsuite/gcc.target/mips/branch-1.c
+++ b/gcc/testsuite/gcc.target/mips/branch-1.c
@@ -2,7 +2,7 @@
    but we test for "bbit" elsewhere.  On other targets, we should implement
    the "if" statements using an "andi" instruction followed by a branch
    on zero.  */
-/* { dg-options "-O2 forbid_cpu=octeon" } */
+/* { dg-options "-O2 forbid_cpu=octeon.*" } */
 
 void bar (void);
 NOMIPS16 void f1 (int x) { if (x & 4) bar (); }
diff --git a/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc/testsuite/gcc.target/mips/dmult-1.c
index 517e43ed54b..f8c0b8b44f1 100644
--- a/gcc/testsuite/gcc.target/mips/dmult-1.c
+++ b/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "forbid_cpu=octeon -mgp64" } */
+/* { dg-options "forbid_cpu=octeon.* -mgp64" } */
 /* { dg-final { scan-assembler "\tdmult\t" } } */
 /* { dg-final { scan-assembler "\tmflo\t" } } */
 /* { dg-final { scan-assembler-not "\tdmul\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc/testsuite/gcc.target/mips/extend-1.c
index 4295106866b..5e9389060c8 100644
--- a/gcc/testsuite/gcc.target/mips/extend-1.c
+++ b/gcc/testsuite/gcc.target/mips/extend-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */
+/* { dg-options "-O -mgp64 forbid_cpu=octeon.*" } */
 /* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */
 /* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */
 /* { dg-final { scan-assembler-not "\tsll\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc/testsuite/gcc.target/mips/mult-1.c
index 43dd08c0b52..96961b0d85c 100644
--- a/gcc/testsuite/gcc.target/mips/mult-1.c
+++ b/gcc/testsuite/gcc.target/mips/mult-1.c
@@ -1,6 +1,6 @@
 /* For SI->DI widening multiplication we should use DINS to combine the two
    halves.  For Octeon use DMUL with explicit widening.  */
-/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */
+/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon.*" } */
 /* { dg-final { scan-assembler "\tdins\t" } } */
 /* { dg-final { scan-assembler-not "\tdsll\t" } } */
 /* { dg-final { scan-assembler-not "\tdsrl\t" } } */