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aarch64-builtins.c (TYPES_SETREGP): Added poly type.

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2016-11-28  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
	(TYPES_GETREGP): Likewise.
	(TYPES_SHIFTINSERTP): Likewise.
	(TYPES_COMBINEP): Likewise.
	(TYPES_STORE1P): Likewise.
	* config/aarch64/aarch64-simd-builtins.def
	(combine): Added poly generator.
	(get_dregoi): Likewise.
	(get_dregci): Likewise.
	(get_dregxi): Likewise.
	(ssli_n): Likewise.
	(ld1): Likewise.
	(st1): Likewise.
	* config/aarch64/arm_neon.h
	(poly64x1x2_t, poly64x1x3_t): New.
	(poly64x1x4_t, poly64x2x2_t): Likewise.
	(poly64x2x3_t, poly64x2x4_t): Likewise.
	(poly64x1_t): Likewise.
	(vcreate_p64, vcombine_p64): Likewise.
	(vdup_n_p64, vdupq_n_p64): Likewise.
	(vld2_p64, vld2q_p64): Likewise.
	(vld3_p64, vld3q_p64): Likewise.
	(vld4_p64, vld4q_p64): Likewise.
	(vld2_dup_p64, vld3_dup_p64): Likewise.
	(vld4_dup_p64, vsli_n_p64): Likewise.
	(vsliq_n_p64, vst1_p64): Likewise.
	(vst1q_p64, vst2_p64): Likewise.
	(vst3_p64, vst4_p64): Likewise.
	(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
	(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
	(vget_lane_p64, vgetq_lane_p64): Likewise.
	(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
	(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
	(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
	(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
	(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
	(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
	(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
	(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
	(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
	(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
	(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
	(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
	(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
	(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
	(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
	(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
	(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
	(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
	(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
	(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
	(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
	(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
	(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
	(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
	(vset_lane_p64, vsetq_lane_p64): Likewise.
	(vget_low_p64, vget_high_p64): Likewise.
	(vcombine_p64, vst2_lane_p64): Likewise.
	(vst3_lane_p64, vst4_lane_p64): Likewise.
	(vst2q_lane_p64, vst3q_lane_p64): Likewise.
	(vst4q_lane_p64, vget_lane_p64): Likewise.
	(vget_laneq_p64, vset_lane_p64): Likewise.
	(vset_laneq_p64, vcopy_lane_p64): Likewise.
	(vcopy_laneq_p64, vdup_n_p64): Likewise.
	(vdupq_n_p64, vdup_lane_p64): Likewise.
	(vdup_laneq_p64, vld1_p64): Likewise.
	(vld1q_p64, vld1_dup_p64): Likewise.
	(vld1q_dup_p64, vld1q_dup_p64): Likewise.
	(vmov_n_p64, vmovq_n_p64): Likewise.
	(vst3q_p64, vst4q_p64): Likewise.
	(vld1_lane_p64, vld1q_lane_p64): Likewise.
	(vst1_lane_p64, vst1q_lane_p64): Likewise.
	(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
	(vdupq_laneq_p64): Likewise.

From-SVN: r242915
This commit is contained in:
Tamar Christina 2016-11-28 12:41:03 +00:00 committed by Tamar Christina
parent f76f4b23a4
commit 159b872453
4 changed files with 1012 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
gcc/ChangeLog
View File

@ -1,3 +1,80 @@
2016-11-28 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_SETREGP): Added poly type.
(TYPES_GETREGP): Likewise.
(TYPES_SHIFTINSERTP): Likewise.
(TYPES_COMBINEP): Likewise.
(TYPES_STORE1P): Likewise.
* config/aarch64/aarch64-simd-builtins.def
(combine): Added poly generator.
(get_dregoi): Likewise.
(get_dregci): Likewise.
(get_dregxi): Likewise.
(ssli_n): Likewise.
(ld1): Likewise.
(st1): Likewise.
* config/aarch64/arm_neon.h
(poly64x1x2_t, poly64x1x3_t): New.
(poly64x1x4_t, poly64x2x2_t): Likewise.
(poly64x2x3_t, poly64x2x4_t): Likewise.
(poly64x1_t): Likewise.
(vcreate_p64, vcombine_p64): Likewise.
(vdup_n_p64, vdupq_n_p64): Likewise.
(vld2_p64, vld2q_p64): Likewise.
(vld3_p64, vld3q_p64): Likewise.
(vld4_p64, vld4q_p64): Likewise.
(vld2_dup_p64, vld3_dup_p64): Likewise.
(vld4_dup_p64, vsli_n_p64): Likewise.
(vsliq_n_p64, vst1_p64): Likewise.
(vst1q_p64, vst2_p64): Likewise.
(vst3_p64, vst4_p64): Likewise.
(__aarch64_vdup_lane_p64, __aarch64_vdup_laneq_p64): Likewise.
(__aarch64_vdupq_lane_p64, __aarch64_vdupq_laneq_p64): Likewise.
(vget_lane_p64, vgetq_lane_p64): Likewise.
(vreinterpret_p8_p64, vreinterpretq_p8_p64): Likewise.
(vreinterpret_p16_p64, vreinterpretq_p16_p64): Likewise.
(vreinterpret_p64_f16, vreinterpret_p64_f64): Likewise.
(vreinterpret_p64_s8, vreinterpret_p64_s16): Likewise.
(vreinterpret_p64_s32, vreinterpret_p64_s64): Likewise.
(vreinterpret_p64_f32, vreinterpret_p64_u8): Likewise.
(vreinterpret_p64_u16, vreinterpret_p64_u32): Likewise.
(vreinterpret_p64_u64, vreinterpret_p64_p8): Likewise.
(vreinterpretq_p64_f64, vreinterpretq_p64_s8): Likewise.
(vreinterpretq_p64_s16, vreinterpretq_p64_s32): Likewise.
(vreinterpretq_p64_s64, vreinterpretq_p64_f16): Likewise.
(vreinterpretq_p64_f32, vreinterpretq_p64_u8): Likewise.
(vreinterpretq_p64_u16, vreinterpretq_p64_u32): Likewise.
(vreinterpretq_p64_u64, vreinterpretq_p64_p8): Likewise.
(vreinterpret_f16_p64, vreinterpretq_f16_p64): Likewise.
(vreinterpret_f32_p64, vreinterpretq_f32_p64): Likewise.
(vreinterpret_f64_p64, vreinterpretq_f64_p64): Likewise.
(vreinterpret_s64_p64, vreinterpretq_s64_p64): Likewise.
(vreinterpret_u64_p64, vreinterpretq_u64_p64): Likewise.
(vreinterpret_s8_p64, vreinterpretq_s8_p64): Likewise.
(vreinterpret_s16_p64, vreinterpret_s32_p64): Likewise.
(vreinterpretq_s32_p64, vreinterpret_u8_p64): Likewise.
(vreinterpret_u16_p64, vreinterpretq_u16_p64): Likewise.
(vreinterpret_u32_p64, vreinterpretq_u32_p64): Likewise.
(vset_lane_p64, vsetq_lane_p64): Likewise.
(vget_low_p64, vget_high_p64): Likewise.
(vcombine_p64, vst2_lane_p64): Likewise.
(vst3_lane_p64, vst4_lane_p64): Likewise.
(vst2q_lane_p64, vst3q_lane_p64): Likewise.
(vst4q_lane_p64, vget_lane_p64): Likewise.
(vget_laneq_p64, vset_lane_p64): Likewise.
(vset_laneq_p64, vcopy_lane_p64): Likewise.
(vcopy_laneq_p64, vdup_n_p64): Likewise.
(vdupq_n_p64, vdup_lane_p64): Likewise.
(vdup_laneq_p64, vld1_p64): Likewise.
(vld1q_p64, vld1_dup_p64): Likewise.
(vld1q_dup_p64, vld1q_dup_p64): Likewise.
(vmov_n_p64, vmovq_n_p64): Likewise.
(vst3q_p64, vst4q_p64): Likewise.
(vld1_lane_p64, vld1q_lane_p64): Likewise.
(vst1_lane_p64, vst1q_lane_p64): Likewise.
(vcopy_laneq_p64, vcopyq_laneq_p64): Likewise.
(vdupq_laneq_p64): Likewise.
2016-11-28 Tamar Christina <tamar.christina@arm.com>
* config/arm/arm_neon.h (vget_lane_p64): New.

32
gcc/config/aarch64/aarch64-builtins.c
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@ -169,6 +169,10 @@ aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
qualifier_none, qualifier_lane_index };
#define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_binop_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_poly, qualifier_none, qualifier_immediate };
#define TYPES_GETREGP (aarch64_types_binop_imm_p_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_immediate };
@ -188,11 +192,20 @@ aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
#define TYPES_SETREG (aarch64_types_ternop_imm_qualifiers)
#define TYPES_SHIFTINSERT (aarch64_types_ternop_imm_qualifiers)
#define TYPES_SHIFTACC (aarch64_types_ternop_imm_qualifiers)
aarch64_types_ternop_s_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_poly, qualifier_immediate};
#define TYPES_SETREGP (aarch64_types_ternop_s_imm_p_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_ternop_s_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate};
#define TYPES_SETREG (aarch64_types_ternop_s_imm_qualifiers)
#define TYPES_SHIFTINSERT (aarch64_types_ternop_s_imm_qualifiers)
#define TYPES_SHIFTACC (aarch64_types_ternop_s_imm_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_ternop_p_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_poly, qualifier_poly, qualifier_poly, qualifier_immediate};
#define TYPES_SHIFTINSERTP (aarch64_types_ternop_p_imm_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
@ -206,6 +219,11 @@ aarch64_types_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none };
#define TYPES_COMBINE (aarch64_types_combine_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_combine_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_poly, qualifier_poly, qualifier_poly };
#define TYPES_COMBINEP (aarch64_types_combine_p_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode };
@ -239,6 +257,10 @@ aarch64_types_bsl_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
qualifier_map_mode | qualifier_pointer to build a pointer to the
element type of the vector. */
static enum aarch64_type_qualifiers
aarch64_types_store1_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_poly };
#define TYPES_STORE1P (aarch64_types_store1_p_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
#define TYPES_STORE1 (aarch64_types_store1_qualifiers)

13
gcc/config/aarch64/aarch64-simd-builtins.def
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@ -40,6 +40,7 @@
10 - CODE_FOR_<name><mode>. */
BUILTIN_VDC (COMBINE, combine, 0)
VAR1 (COMBINEP, combine, 0, di)
BUILTIN_VB (BINOP, pmul, 0)
BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
@ -68,14 +69,23 @@
BUILTIN_VDC (GETREG, get_dregoi, 0)
BUILTIN_VDC (GETREG, get_dregci, 0)
BUILTIN_VDC (GETREG, get_dregxi, 0)
VAR1 (GETREGP, get_dregoi, 0, di)
VAR1 (GETREGP, get_dregci, 0, di)
VAR1 (GETREGP, get_dregxi, 0, di)
/* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */
BUILTIN_VQ (GETREG, get_qregoi, 0)
BUILTIN_VQ (GETREG, get_qregci, 0)
BUILTIN_VQ (GETREG, get_qregxi, 0)
VAR1 (GETREGP, get_qregoi, 0, v2di)
VAR1 (GETREGP, get_qregci, 0, v2di)
VAR1 (GETREGP, get_qregxi, 0, v2di)
/* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */
BUILTIN_VQ (SETREG, set_qregoi, 0)
BUILTIN_VQ (SETREG, set_qregci, 0)
BUILTIN_VQ (SETREG, set_qregxi, 0)
VAR1 (SETREGP, set_qregoi, 0, v2di)
VAR1 (SETREGP, set_qregci, 0, v2di)
VAR1 (SETREGP, set_qregxi, 0, v2di)
/* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
BUILTIN_VDC (LOADSTRUCT, ld2, 0)
BUILTIN_VDC (LOADSTRUCT, ld3, 0)
@ -224,6 +234,7 @@
BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
/* Implemented by aarch64_<sur>qshl<u>_n<mode>. */
BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
@ -416,9 +427,11 @@
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
BUILTIN_VALL_F16 (LOAD1, ld1, 0)
VAR1(STORE1P, ld1, 0, v2di)
/* Implemented by aarch64_st1<VALL_F16:mode>. */
BUILTIN_VALL_F16 (STORE1, st1, 0)
VAR1(STORE1P, st1, 0, v2di)
/* Implemented by fma<mode>4. */
BUILTIN_VHSDF (TERNOP, fma, 4)

896
gcc/config/aarch64/arm_neon.h
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