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re PR lto/59326 (FAIL: gcc.dg/vect/vect-simd-clone-*.c)

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PR lto/59326
	* gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
	* lib/target-supports.exp (check_effective_target_avx2): ... here.
	(check_effective_target_vect_simd_clones): New.
	* gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
	vect_simd_clones.
	* gcc.dg/vect/vect-simd-clone-2.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-3.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-4.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-5.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-6.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-7.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-8.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-9.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-10.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-11.c: Likewise.
	* gcc.dg/vect/vect-simd-clone-12.c: Likewise.

From-SVN: r205606
This commit is contained in:
Jakub Jelinek 2013-12-02 23:39:12 +01:00 committed by Jakub Jelinek
parent 858c19053b
commit 165b9e9352
15 changed files with 70 additions and 12 deletions
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20
gcc/testsuite/ChangeLog
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@ -1,3 +1,23 @@
2013-12-02 Jakub Jelinek <jakub@redhat.com>
PR lto/59326
* gcc.target/i386/i386.exp (check_effective_target_avx2): Move to...
* lib/target-supports.exp (check_effective_target_avx2): ... here.
(check_effective_target_vect_simd_clones): New.
* gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target
vect_simd_clones.
* gcc.dg/vect/vect-simd-clone-2.c: Likewise.
* gcc.dg/vect/vect-simd-clone-3.c: Likewise.
* gcc.dg/vect/vect-simd-clone-4.c: Likewise.
* gcc.dg/vect/vect-simd-clone-5.c: Likewise.
* gcc.dg/vect/vect-simd-clone-6.c: Likewise.
* gcc.dg/vect/vect-simd-clone-7.c: Likewise.
* gcc.dg/vect/vect-simd-clone-8.c: Likewise.
* gcc.dg/vect/vect-simd-clone-9.c: Likewise.
* gcc.dg/vect/vect-simd-clone-10.c: Likewise.
* gcc.dg/vect/vect-simd-clone-11.c: Likewise.
* gcc.dg/vect/vect-simd-clone-12.c: Likewise.
2013-12-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
* gcc.dg/pr56997-4.c: New testcase.

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */
/* { dg-additional-sources vect-simd-clone-10a.c } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */
/* { dg-additional-sources vect-simd-clone-12a.c } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

1
gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c
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@ -1,3 +1,4 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-additional-options "-fopenmp-simd" } */
/* { dg-additional-options "-mavx" { target avx_runtime } } */

12
gcc/testsuite/gcc.target/i386/i386.exp
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@ -209,18 +209,6 @@ proc check_effective_target_lzcnt { } {
} "-mlzcnt" ]
}
# Return 1 if avx2 instructions can be compiled.
proc check_effective_target_avx2 { } {
return [check_no_compiler_messages avx2 object {
typedef long long __v4di __attribute__ ((__vector_size__ (32)));
__v4di
mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
{
return __builtin_ia32_andnotsi256 (__X, __Y);
}
} "-O0 -mavx2" ]
}
# Return 1 if bmi instructions can be compiled.
proc check_effective_target_bmi { } {
return [check_no_compiler_messages bmi object {

38
gcc/testsuite/lib/target-supports.exp
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@ -2146,6 +2146,32 @@ proc check_effective_target_vect_floatuint_cvt { } {
return $et_vect_floatuint_cvt_saved
}
# Return 1 if the target supports #pragma omp declare simd, 0 otherwise.
#
# This won't change for different subtargets so cache the result.
proc check_effective_target_vect_simd_clones { } {
global et_vect_simd_clones_saved
if [info exists et_vect_simd_clones_saved] {
verbose "check_effective_target_vect_simd_clones: using cached result" 2
} else {
set et_vect_simd_clones_saved 0
if { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
# On i?86/x86_64 #pragma omp declare simd builds a sse2, avx and
# avx2 clone. Only the right clone for the specified arch will be
# chosen, but still we need to at least be able to assemble
# avx2.
if { [check_effective_target_avx2] } {
set et_vect_simd_clones_saved 1
}
}
}
verbose "check_effective_target_vect_simd_clones: returning $et_vect_simd_clones_saved" 2
return $et_vect_simd_clones_saved
}
# Return 1 if this is a AArch64 target supporting big endian
proc check_effective_target_aarch64_big_endian { } {
return [check_no_compiler_messages aarch64_big_endian assembly {
@ -5106,6 +5132,18 @@ proc check_effective_target_avx { } {
} "-O2 -mavx" ]
}
# Return 1 if avx2 instructions can be compiled.
proc check_effective_target_avx2 { } {
return [check_no_compiler_messages avx2 object {
typedef long long __v4di __attribute__ ((__vector_size__ (32)));
__v4di
mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
{
return __builtin_ia32_andnotsi256 (__X, __Y);
}
} "-O0 -mavx2" ]
}
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {