sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGET_ARCH64.
* config/sparc/sparc.md (define_insn addx_extend): Rename to addx_extend_sp64, only allow when TARGET_ARCH64. (define_insn addx_extend_sp32 and split): Version that works when not TARGET_ARCH64. (define_insn subx_extend): Likewise. (define_split adddi3 and subdi3 with zero extension): Fixup and correct bugs when not TARGET_ARCH64. From-SVN: r21677
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16cf811987
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@ -1,3 +1,13 @@
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Tue Aug 11 22:42:01 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.md (define_insn addx_extend): Rename to
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addx_extend_sp64, only allow when TARGET_ARCH64.
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(define_insn addx_extend_sp32 and split): Version that works when
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not TARGET_ARCH64.
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(define_insn subx_extend): Likewise.
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(define_split adddi3 and subdi3 with zero extension): Fixup and
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correct bugs when not TARGET_ARCH64.
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Tue Aug 11 16:04:34 1998 John Carr <jfc@mit.edu>
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* except.c (set_exception_lang_code, set_exception_version_code):
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@ -4444,12 +4444,34 @@ movtf_is_ok:
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[(set_attr "type" "unary")
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(set_attr "length" "1")])
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(define_insn "*addx_extend"
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(define_insn "*addx_extend_sp32"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
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(match_operand:SI 2 "arith_operand" "rI"))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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""
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"! TARGET_ARCH64"
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"#"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
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(match_operand:SI 2 "arith_operand" ""))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"! TARGET_ARCH64 && reload_completed"
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[(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
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(set (match_dup 4) (const_int 0))]
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"operands[3] = gen_lowpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[1]);")
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(define_insn "*addx_extend_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
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(match_operand:SI 2 "arith_operand" "rI"))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"TARGET_ARCH64"
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"addx\\t%r1, %2, %0"
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[(set_attr "type" "unary")
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(set_attr "length" "1")])
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@ -4464,15 +4486,37 @@ movtf_is_ok:
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[(set_attr "type" "unary")
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(set_attr "length" "1")])
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(define_insn "*subx_extend_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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(match_operand:SI 2 "arith_operand" "rI"))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"TARGET_ARCH64"
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"subx\\t%r1, %2, %0"
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[(set_attr "type" "unary")
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(set_attr "length" "1")])
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(define_insn "*subx_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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(match_operand:SI 2 "arith_operand" "rI"))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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""
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"subx\\t%r1, %2, %0"
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"! TARGET_ARCH64"
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"#"
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[(set_attr "type" "unary")
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(set_attr "length" "1")])
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(set_attr "length" "2")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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(match_operand:SI 2 "arith_operand" "rI"))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"! TARGET_ARCH64 && reload_completed"
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[(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
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(set (match_dup 4) (const_int 0))]
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"operands[3] = gen_lowpart (SImode, operands[0]);
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operands[4] = gen_highpart (SImode, operands[0]);")
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;; This is only for splits at the moment.
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(define_insn ""
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@ -4487,8 +4531,8 @@ movtf_is_ok:
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(match_operand:DI 2 "register_operand" "r")))
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(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
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(match_operand:DI 2 "register_operand" "r")))
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(clobber (reg:CC 100))]
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"! TARGET_ARCH64"
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"#"
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@ -4501,14 +4545,17 @@ movtf_is_ok:
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(match_operand:DI 2 "register_operand" "")))
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(clobber (reg:CC 100))]
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"! TARGET_ARCH64"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
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(const_int 0)))
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(set (match_dup 0)
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[(parallel [(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
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(const_int 0)))
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(set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
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(set (match_dup 6)
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(plus:SI (plus:SI (match_dup 4) (const_int 0))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"operands[3] = gen_lowpart (SImode, operands[2]);
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operands[4] = gen_highpart (SImode, operands[2]);")
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operands[4] = gen_highpart (SImode, operands[2]);
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operands[5] = gen_lowpart (SImode, operands[0]);
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operands[6] = gen_highpart (SImode, operands[0]);")
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(define_insn "*adddi3_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -4672,14 +4719,17 @@ movtf_is_ok:
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(zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
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(clobber (reg:CC 100))]
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"! TARGET_ARCH64"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
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(const_int 0)))
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(set (match_dup 0)
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(plus:SI (plus:SI (match_dup 4) (const_int 0))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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[(parallel [(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
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(const_int 0)))
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(set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
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(set (match_dup 6)
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(minus:SI (minus:SI (match_dup 4) (const_int 0))
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(ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
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"operands[3] = gen_lowpart (SImode, operands[1]);
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operands[4] = gen_highpart (SImode, operands[1]);")
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operands[4] = gen_highpart (SImode, operands[1]);
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operands[5] = gen_lowpart (SImode, operands[0]);
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operands[6] = gen_highpart (SImode, operands[0]);")
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(define_insn "*subdi3_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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