From 16d5eaa1b5666b1c263ab5869e1d9b28cd7b0a99 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Mon, 24 Nov 2014 19:27:29 +0000 Subject: [PATCH] re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64) 2014-11-24 Michael Meissner PR target/63965 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set Altivec & -16 mask if the type is not valid for Altivec registers. (rs6000_secondary_reload_memory): Add support for ((reg + const) + reg) that occurs during push_reload processing. * config/rs6000/altivec.md (altivec_mov): Add instruction alternative for moving constant vectors which are easy altivec constants to GPRs. Set the length attribute each of the alternatives. From-SVN: r218028 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/rs6000/altivec.md | 8 +++++--- gcc/config/rs6000/rs6000.c | 14 +++++++++++++- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5df9ef66bd4..5db7497608b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,16 @@ 2014-11-24 Michael Meissner PR target/63965 + * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set + Altivec & -16 mask if the type is not valid for Altivec registers. + (rs6000_secondary_reload_memory): Add support for ((reg + const) + + reg) that occurs during push_reload processing. + + * config/rs6000/altivec.md (altivec_mov): Add instruction + alternative for moving constant vectors which are easy altivec + constants to GPRs. Set the length attribute each of the + alternatives. + * config/rs6000/rs6000-cpus.def: Undo November 21st changes, a work in progress patch was committed instead of the fixes for 63965. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index d46ef191409..3f52ca0c585 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -189,8 +189,8 @@ ;; Vector move instructions. (define_insn "*altivec_mov" - [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v") - (match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W"))] + [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r") + (match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W,W"))] "VECTOR_MEM_ALTIVEC_P (mode) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" @@ -205,10 +205,12 @@ case 5: return "#"; case 6: return "vxor %0,%0,%0"; case 7: return output_vec_const_move (operands); + case 8: return "#"; default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")]) + [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*") + (set_attr "length" "4,4,4,20,20,20,4,8,32")]) ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode ;; is for unions. However for plain data movement, slightly favor the vector diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ea3e5112014..a87e762e56d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2505,7 +2505,8 @@ rs6000_setup_reg_addr_masks (void) /* VMX registers can do (REG & -16) and ((REG+REG) & -16) addressing on 128-bit types. */ - if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16) + if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16 + && (addr_mask & RELOAD_REG_VALID) != 0) addr_mask |= RELOAD_REG_AND_M16; reg_addr[m].addr_mask[rc] = addr_mask; @@ -16652,6 +16653,17 @@ rs6000_secondary_reload_memory (rtx addr, } } + /* (plus (plus (reg) (constant)) (reg)) is also generated during + push_reload processing, so handle it now. */ + else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1)) + { + if ((addr_mask & RELOAD_REG_INDEXED) == 0) + { + extra_cost = 1; + type = "indexed #2"; + } + } + else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0))) { fail_msg = "no base register #2";