ia64.c (ia64_expand_atomic_op): New.
* config/ia64/ia64.c (ia64_expand_atomic_op): New. * config/ia64/ia64-protos.h: Declare it. * config/ia64/sync.md (I124MODE, FETCHOP, fetchop_name): New. (sync_add<I48MODE>, sync_old_add<I48MODE>): Remove. (sync_<FETCHOP><IMODE>, sync_nand<IMODE>): New. (sync_old_<FETCHOP><IMODE>, sync_old_nand<IMODE>): New. (sync_new_<FETCHOP><IMODE>, sync_new_nand<IMODE>): New. (cmpxchg_rel_<I124MODE>): Split from cmpxchg_acq_<IMODE>. Zero extend result; use release semantics. (cmpxchg_rel_di): Rename from cmpxchg_acq_<IMODE>; use release. (sync_val_compare_and_swap_<IMODE>): Update to match. From-SVN: r99527
This commit is contained in:
parent
64552cd790
commit
16df4ee6c2
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@ -1,3 +1,17 @@
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2005-05-10 Richard Henderson <rth@redhat.com>
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* config/ia64/ia64.c (ia64_expand_atomic_op): New.
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* config/ia64/ia64-protos.h: Declare it.
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* config/ia64/sync.md (I124MODE, FETCHOP, fetchop_name): New.
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(sync_add<I48MODE>, sync_old_add<I48MODE>): Remove.
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(sync_<FETCHOP><IMODE>, sync_nand<IMODE>): New.
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(sync_old_<FETCHOP><IMODE>, sync_old_nand<IMODE>): New.
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(sync_new_<FETCHOP><IMODE>, sync_new_nand<IMODE>): New.
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(cmpxchg_rel_<I124MODE>): Split from cmpxchg_acq_<IMODE>. Zero
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extend result; use release semantics.
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(cmpxchg_rel_di): Rename from cmpxchg_acq_<IMODE>; use release.
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(sync_val_compare_and_swap_<IMODE>): Update to match.
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2005-05-10 Richard Henderson <rth@redhat.com>
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* optabs.c (expand_compare_and_swap_loop): Don't clobber old value
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@ -51,6 +51,7 @@ extern bool ia64_expand_vecint_minmax (enum rtx_code, enum machine_mode, rtx[]);
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extern void ia64_expand_call (rtx, rtx, rtx, int);
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extern void ia64_split_call (rtx, rtx, rtx, rtx, rtx, int, int);
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extern void ia64_reload_gp (void);
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extern void ia64_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx);
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extern HOST_WIDE_INT ia64_initial_elimination_offset (int, int);
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extern void ia64_expand_prologue (void);
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@ -1662,6 +1662,111 @@ ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
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if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
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ia64_reload_gp ();
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}
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/* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
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This differs from the generic code in that we know about the zero-extending
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properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
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also know that ld.acq+cmpxchg.rel equals a full barrier.
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The loop we want to generate looks like
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cmp_reg = mem;
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label:
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old_reg = cmp_reg;
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new_reg = cmp_reg op val;
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cmp_reg = compare-and-swap(mem, old_reg, new_reg)
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if (cmp_reg != old_reg)
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goto label;
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Note that we only do the plain load from memory once. Subsequent
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iterations use the value loaded by the compare-and-swap pattern. */
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void
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ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
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rtx old_dst, rtx new_dst)
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{
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enum machine_mode mode = GET_MODE (mem);
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rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
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enum insn_code icode;
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/* Special case for using fetchadd. */
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if ((mode == SImode || mode == DImode) && fetchadd_operand (val, mode))
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{
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if (!old_dst)
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old_dst = gen_reg_rtx (mode);
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emit_insn (gen_memory_barrier ());
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if (mode == SImode)
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icode = CODE_FOR_fetchadd_acq_si;
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else
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icode = CODE_FOR_fetchadd_acq_di;
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emit_insn (GEN_FCN (icode) (old_dst, mem, val));
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if (new_dst)
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{
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new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
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true, OPTAB_WIDEN);
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if (new_reg != new_dst)
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emit_move_insn (new_dst, new_reg);
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}
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return;
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}
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/* Because of the volatile mem read, we get an ld.acq, which is the
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front half of the full barrier. The end half is the cmpxchg.rel. */
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gcc_assert (MEM_VOLATILE_P (mem));
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old_reg = gen_reg_rtx (DImode);
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cmp_reg = gen_reg_rtx (DImode);
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label = gen_label_rtx ();
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if (mode != DImode)
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{
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val = simplify_gen_subreg (DImode, val, mode, 0);
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emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
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}
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else
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emit_move_insn (cmp_reg, mem);
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emit_label (label);
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ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
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emit_move_insn (old_reg, cmp_reg);
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emit_move_insn (ar_ccv, cmp_reg);
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if (old_dst)
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emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
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new_reg = cmp_reg;
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if (code == NOT)
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{
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new_reg = expand_simple_unop (DImode, NOT, new_reg, NULL_RTX, true);
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code = AND;
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}
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new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
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true, OPTAB_DIRECT);
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if (mode != DImode)
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new_reg = gen_lowpart (mode, new_reg);
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if (new_dst)
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emit_move_insn (new_dst, new_reg);
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switch (mode)
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{
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case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
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case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
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case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
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case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
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default:
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gcc_unreachable ();
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}
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emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
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emit_cmp_and_jump_insns (cmp_reg, old_reg, EQ, NULL, DImode, true, label);
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}
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/* Begin the assembly file. */
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@ -20,9 +20,13 @@
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;; Boston, MA 02111-1307, USA.
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(define_mode_macro IMODE [QI HI SI DI])
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(define_mode_macro I124MODE [QI HI SI])
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(define_mode_macro I48MODE [SI DI])
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(define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
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(define_code_macro FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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(define_insn "memory_barrier"
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[(set (mem:BLK (match_scratch:DI 0 "X"))
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"mf"
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[(set_attr "itanium_class" "syst_m")])
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(define_expand "sync_add<mode>"
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[(match_operand:I48MODE 0 "memory_operand" "")
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(match_operand:I48MODE 1 "general_operand" "")]
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""
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{
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rtx tmp;
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if (!fetchadd_operand (operands[1], <MODE>mode))
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FAIL;
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tmp = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_memory_barrier ());
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emit_insn (gen_fetchadd_acq_<mode> (tmp, operands[0], operands[1]));
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DONE;
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})
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(define_expand "sync_old_add<mode>"
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[(match_operand:I48MODE 0 "gr_register_operand" "")
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(match_operand:I48MODE 1 "memory_operand" "")
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(match_operand:I48MODE 2 "general_operand" "")]
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""
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{
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if (!fetchadd_operand (operands[2], <MODE>mode))
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FAIL;
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emit_insn (gen_memory_barrier ());
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emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "fetchadd_acq_<mode>"
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[(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
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(match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
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"fetchadd<modesuffix>.acq %0 = %1, %2"
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[(set_attr "itanium_class" "sem")])
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(define_expand "sync_<fetchop_name><mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "")
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(FETCHOP:IMODE (match_dup 0)
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(match_operand:IMODE 1 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL);
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DONE;
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})
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(define_expand "sync_nand<mode>"
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[(set (match_operand:IMODE 0 "memory_operand" "")
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(and:IMODE (not:IMODE (match_dup 0))
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(match_operand:IMODE 1 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL);
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DONE;
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})
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(define_expand "sync_old_<fetchop_name><mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(FETCHOP:IMODE
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(match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL);
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DONE;
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})
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(define_expand "sync_old_nand<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(and:IMODE
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(not:IMODE (match_operand:IMODE 1 "memory_operand" ""))
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(match_operand:IMODE 2 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL);
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DONE;
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})
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(define_expand "sync_new_<fetchop_name><mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(FETCHOP:IMODE
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(match_operand:IMODE 1 "memory_operand" "")
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(match_operand:IMODE 2 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0]);
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DONE;
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})
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(define_expand "sync_new_nand<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "")
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(and:IMODE
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(not:IMODE (match_operand:IMODE 1 "memory_operand" ""))
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(match_operand:IMODE 2 "general_operand" "")))]
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""
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{
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ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0]);
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DONE;
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})
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(define_expand "sync_compare_and_swap<mode>"
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[(match_operand:IMODE 0 "gr_register_operand" "")
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(match_operand:IMODE 1 "memory_operand" "")
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""
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{
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rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
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rtx dst;
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convert_move (ccv, operands[2], 1);
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dst = operands[0];
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if (GET_MODE (dst) != DImode)
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dst = gen_reg_rtx (DImode);
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emit_insn (gen_memory_barrier ());
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emit_insn (gen_cmpxchg_acq_<mode> (operands[0], operands[1],
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ccv, operands[3]));
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emit_insn (gen_cmpxchg_rel_<mode> (dst, operands[1], ccv, operands[3]));
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if (dst != operands[0])
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emit_move_insn (operands[0], gen_lowpart (<MODE>mode, dst));
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DONE;
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})
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(define_insn "cmpxchg_acq_<mode>"
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[(set (match_operand:IMODE 0 "gr_register_operand" "=r")
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(match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
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(define_insn "cmpxchg_rel_<mode>"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(zero_extend:DI
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(match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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(set (match_dup 1)
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(unspec:IMODE [(match_dup 1)
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(unspec:I124MODE
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[(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:IMODE 3 "gr_register_operand" "r")]
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(match_operand:I124MODE 3 "gr_register_operand" "r")]
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UNSPEC_CMPXCHG_ACQ))]
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""
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"cmpxchg<modesuffix>.acq %0 = %1, %3, %2"
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"cmpxchg<modesuffix>.rel %0 = %1, %3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "cmpxchg_rel_di"
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[(set (match_operand:DI 0 "gr_register_operand" "=r")
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(match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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(set (match_dup 1)
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(unspec:DI [(match_dup 1)
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(match_operand:DI 2 "ar_ccv_reg_operand" "")
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(match_operand:DI 3 "gr_register_operand" "r")]
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UNSPEC_CMPXCHG_ACQ))]
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""
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"cmpxchg8.rel %0 = %1, %3, %2"
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[(set_attr "itanium_class" "sem")])
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(define_insn "sync_lock_test_and_set<mode>"
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