* config/arm/arm.md (Thumb-1 ldrsb peephole): New.
From-SVN: r162021
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@ -11,6 +11,8 @@
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* config/arm/arm.md (addsi3_cbranch): Switch alternatives 0 and 1.
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* config/arm/arm.md (Thumb-1 ldrsb peephole): New.
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2010-07-09 Richard Guenther <rguenther@suse.de>
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* gimple.c (struct type_fixup_s): New struct and VEC type.
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@ -4615,6 +4615,27 @@
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operands[3] = change_address (operands[1], QImode, addr);
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})
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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(plus:SI (match_dup 0) (match_operand 1 "const_int_operand")))
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(set (match_operand:SI 2 "register_operand" "") (const_int 0))
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(set (match_operand:SI 3 "register_operand" "")
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(sign_extend:SI (match_operand:QI 4 "memory_operand" "")))]
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"TARGET_THUMB1
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&& GET_CODE (XEXP (operands[4], 0)) == PLUS
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&& rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0))
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&& rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1))
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&& (peep2_reg_dead_p (3, operands[0])
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|| rtx_equal_p (operands[0], operands[3]))
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&& (peep2_reg_dead_p (3, operands[2])
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|| rtx_equal_p (operands[2], operands[3]))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 3) (sign_extend:SI (match_dup 4)))]
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{
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rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
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operands[4] = change_address (operands[4], QImode, addr);
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})
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(define_insn "thumb1_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=l,l,l")
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(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))]
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