re PR target/54212 (ARM: invalid instruction (vdupeq.32) generated)
Fix PR target/54212 2012-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> Backport from mainline. 2012-08-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> PR target/54212 * config/arm/neon.md (vec_set<mode>_internal VD,VQ): Do not mark as predicable. Adjust asm template. (vec_setv2di_internal): Likewise. (vec_extract<mode> VD, VQ): Likewise. (vec_extractv2di): Likewise. (neon_vget_lane<mode>_sext_internal VD, VQ): Likewise. (neon_vset_lane<mode>_sext_internal VD, VQ): Likewise. (neon_vdup_n<mode> VX, V32): Likewise. (neon_vdup_nv2di): Likewise. From-SVN: r190527
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@ -1,3 +1,19 @@
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2012-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
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Backport from mainline.
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2012-08-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
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PR target/54212
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* config/arm/neon.md (vec_set<mode>_internal VD,VQ): Do not
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mark as predicable. Adjust asm template.
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(vec_setv2di_internal): Likewise.
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(vec_extract<mode> VD, VQ): Likewise.
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(vec_extractv2di): Likewise.
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(neon_vget_lane<mode>_sext_internal VD, VQ): Likewise.
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(neon_vset_lane<mode>_sext_internal VD, VQ): Likewise.
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(neon_vdup_n<mode> VX, V32): Likewise.
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(neon_vdup_nv2di): Likewise.
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2012-08-17 Walter Lee <walt@tilera.com>
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Backport from mainline
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@ -435,10 +435,9 @@
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elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
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operands[2] = GEN_INT (elt);
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return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
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return "vmov.<V_sz_elem>\t%P0[%c2], %1";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_mcr")])
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[(set_attr "neon_type" "neon_mcr")])
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(define_insn "vec_set<mode>_internal"
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[(set (match_operand:VQ 0 "s_register_operand" "=w")
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@ -461,10 +460,9 @@
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operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
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operands[2] = GEN_INT (elt);
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return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
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return "vmov.<V_sz_elem>\t%P0[%c2], %1";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_mcr")]
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[(set_attr "neon_type" "neon_mcr")]
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)
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(define_insn "vec_setv2di_internal"
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@ -481,10 +479,9 @@
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operands[0] = gen_rtx_REG (DImode, regno);
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return "vmov%?\t%P0, %Q1, %R1";
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return "vmov\t%P0, %Q1, %R1";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_mcr_2_mcrr")]
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[(set_attr "neon_type" "neon_mcr_2_mcrr")]
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)
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(define_expand "vec_set<mode>"
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@ -512,10 +509,9 @@
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elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
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operands[2] = GEN_INT (elt);
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}
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return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
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return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "vec_extract<mode>"
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@ -536,10 +532,9 @@
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operands[1] = gen_rtx_REG (<V_HALF>mode, regno + hi);
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operands[2] = GEN_INT (elt);
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return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
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return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "vec_extractv2di"
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@ -553,10 +548,9 @@
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operands[1] = gen_rtx_REG (DImode, regno);
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return "vmov%?\t%Q0, %R0, %P1 @ v2di";
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return "vmov\t%Q0, %R0, %P1 @ v2di";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_int_1")]
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[(set_attr "neon_type" "neon_int_1")]
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)
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(define_expand "vec_init<mode>"
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@ -2581,10 +2575,9 @@
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elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
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operands[2] = GEN_INT (elt);
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}
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return "vmov%?.s<V_sz_elem>\t%0, %P1[%c2]";
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return "vmov.s<V_sz_elem>\t%0, %P1[%c2]";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vget_lane<mode>_zext_internal"
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@ -2601,10 +2594,9 @@
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elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
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operands[2] = GEN_INT (elt);
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}
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return "vmov%?.u<V_sz_elem>\t%0, %P1[%c2]";
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return "vmov.u<V_sz_elem>\t%0, %P1[%c2]";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vget_lane<mode>_sext_internal"
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@ -2627,12 +2619,11 @@
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ops[0] = operands[0];
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ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
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ops[2] = GEN_INT (elt_adj);
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output_asm_insn ("vmov%?.s<V_sz_elem>\t%0, %P1[%c2]", ops);
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output_asm_insn ("vmov.s<V_sz_elem>\t%0, %P1[%c2]", ops);
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return "";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vget_lane<mode>_zext_internal"
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@ -2655,12 +2646,11 @@
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ops[0] = operands[0];
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ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
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ops[2] = GEN_INT (elt_adj);
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output_asm_insn ("vmov%?.u<V_sz_elem>\t%0, %P1[%c2]", ops);
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output_asm_insn ("vmov.u<V_sz_elem>\t%0, %P1[%c2]", ops);
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return "";
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}
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_expand "neon_vget_lane<mode>"
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@ -2781,10 +2771,9 @@
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[(set (match_operand:VX 0 "s_register_operand" "=w")
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(vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
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"TARGET_NEON"
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"vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
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"vdup.<V_sz_elem>\t%<V_reg>0, %1"
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;; Assume this schedules like vmov.
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vdup_n<mode>"
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(vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
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"TARGET_NEON"
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"@
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vdup%?.<V_sz_elem>\t%<V_reg>0, %1
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vdup%?.<V_sz_elem>\t%<V_reg>0, %y1"
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vdup.<V_sz_elem>\t%<V_reg>0, %1
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vdup.<V_sz_elem>\t%<V_reg>0, %y1"
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;; Assume this schedules like vmov.
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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[(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_expand "neon_vdup_ndi"
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@ -2814,10 +2802,9 @@
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(vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
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"TARGET_NEON"
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"@
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vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
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vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
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[(set_attr "predicable" "yes")
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(set_attr "length" "8")
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vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1
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vmov\t%e0, %P1\;vmov\t%f0, %P1"
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[(set_attr "length" "8")
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(set_attr "neon_type" "neon_bp_simple")]
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)
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