docs: Add 'S' to Machine Constraints for RISC-V
It was undocument before, but it might used in linux kernel for resolve code model issue, so LLVM community suggest we should document that, so that make it become supported/documented/non-internal machine constraints. gcc/ChangeLog: PR target/101275 * config/riscv/constraints.md ("S"): Update description and remove @internal. * doc/md.texi (Machine Constraints): Document the 'S' constraints for RISC-V.
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@ -67,8 +67,7 @@
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(match_test "GET_CODE(XEXP(op,0)) == REG")))
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(define_constraint "S"
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"@internal
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A constant call address."
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"A constraint that matches an absolute symbolic address."
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(match_operand 0 "absolute_symbolic_operand"))
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(define_constraint "U"
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@ -3536,6 +3536,9 @@ A 5-bit unsigned immediate for CSR access instructions.
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@item A
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An address that is held in a general-purpose register.
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@item S
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A constraint that matches an absolute symbolic address.
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@end table
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@item RX---@file{config/rx/constraints.md}
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