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rs6000.h (CONST_OK_FOR_LETTER_P): Do not assume 32-bit CONST_INT. 

* rs6000.h (CONST_OK_FOR_LETTER_P): Do not assume 32-bit CONST_INT.
        * rs6000.c (u_short_cint_operand, add_operand, logical_operand,
        non_add_cint_operand, non_logical_cint_operand): Likewise.
        (get_issue_rate): Add CPU_PPC604E case.
        * rs6000.md (movdi, !TARGET_POWERPC64 splitters): Handle 64-bit hosts.

From-SVN: r24689
This commit is contained in:
David Edelsohn 1999-01-15 22:40:37 +00:00 committed by David Edelsohn
parent 5a86d174cb
commit 19684119cb
4 changed files with 24 additions and 9 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
Fri Jan 15 22:30:04 1999 David Edelsohn <edelsohn@mhpcc.edu>
* rs6000.h (CONST_OK_FOR_LETTER_P): Do not assume 32-bit CONST_INT.
* rs6000.c (u_short_cint_operand, add_operand, logical_operand,
non_add_cint_operand, non_logical_cint_operand): Likewise.
(get_issue_rate): Add CPU_PPC604E case.
* rs6000.md (movdi, !TARGET_POWERPC64 splitters): Handle 64-bit hosts.
Fri Jan 15 18:42:12 1999 Richard Henderson <rth@cygnus.com>
* expr.c (queued_subexp_p): Make public.

16
gcc/config/rs6000/rs6000.c
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@ -507,8 +507,8 @@ u_short_cint_operand (op, mode)
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return ((GET_CODE (op) == CONST_INT
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0));
return (GET_CODE (op) == CONST_INT
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0);
}
/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
@ -854,7 +854,8 @@ add_operand (op, mode)
enum machine_mode mode;
{
return (reg_or_short_operand (op, mode)
|| (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
|| (GET_CODE (op) == CONST_INT
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0));
}
/* Return 1 if OP is a constant but not a valid add_operand. */
@ -866,7 +867,7 @@ non_add_cint_operand (op, mode)
{
return (GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
&& (INTVAL (op) & 0xffff) != 0);
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
}
/* Return 1 if the operand is a non-special register or a constant that
@ -880,7 +881,7 @@ logical_operand (op, mode)
return (gpc_reg_operand (op, mode)
|| (GET_CODE (op) == CONST_INT
&& ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
|| (INTVAL (op) & 0xffff) == 0)));
|| (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
}
/* Return 1 if C is a constant that is not a logical operand (as
@ -893,7 +894,7 @@ non_logical_cint_operand (op, mode)
{
return (GET_CODE (op) == CONST_INT
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
&& (INTVAL (op) & 0xffff) != 0);
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
}
/* Return 1 if C is a constant that can be encoded in a mask on the
@ -5132,6 +5133,8 @@ int get_issue_rate()
return 2;
case CPU_PPC604:
return 4;
case CPU_PPC604E:
return 4;
case CPU_PPC620:
return 4;
default:
@ -5139,7 +5142,6 @@ int get_issue_rate()
}
}
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.

2
gcc/config/rs6000/rs6000.h
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@ -1075,7 +1075,7 @@ enum reg_class
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
: (C) == 'J' ? ((VALUE) & 0xffff) == 0 \
: (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
: (C) == 'L' ? mask_constant (VALUE) \
: (C) == 'M' ? (VALUE) > 31 \

7
gcc/config/rs6000/rs6000.md
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@ -6127,13 +6127,18 @@
{
operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
#if HOST_BITS_PER_WIDE_INT == 32
operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
#else
operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
operands[1] = INTVAL (operands[1]) & 0xffffffff;
#endif
}")
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_double_operand" ""))]
"! TARGET_POWERPC64 && reload_completed"
"HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
"