[arm] Add new isa quirk bit for Cortex-M3 ldrd issue.
With the new data structures it is trivial to add a new field and we aren't (too) limited as to the number we have. This patch adds a new bit to describe the need for a particular compiler behaviour modification: in this case a quirk in the cortex-m3. * arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd. (ISA_ALL_QUIRKS): New macro. * arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list. * arm.c (isa_quirkbits): New feature-list bitmap. (arm_configure_build_target): Ignore quirk bits when comparing an architecture feature list with a CPU feature list. (arm_option_override): Initialize_isa_quirkbits. If the user has not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the feature if isa_quirk_cm3_ldrd appears in the isa feature list. From-SVN: r243701
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@ -1,3 +1,15 @@
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2016-12-15 Richard Earnshaw <rearnsha@arm.com>
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* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
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(ISA_ALL_QUIRKS): New macro.
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* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
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* arm.c (isa_quirkbits): New feature-list bitmap.
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(arm_configure_build_target): Ignore quirk bits when comparing an
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architecture feature list with a CPU feature list.
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(arm_option_override): Initialize_isa_quirkbits. If the user has
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not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
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feature if isa_quirk_cm3_ldrd appears in the isa feature list.
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2016-12-15 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (arm_option_override): Use arm_active_target as source of
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@ -160,7 +160,7 @@ ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv
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ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
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ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
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ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
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ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
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ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
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ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
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/* V7 big.LITTLE implementations */
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@ -3056,6 +3056,7 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
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}
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static sbitmap isa_fpubits;
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static sbitmap isa_quirkbits;
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/* Configure a build target TARGET from the user-specified options OPTS and
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OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
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@ -3097,6 +3098,8 @@ arm_configure_build_target (struct arm_build_target *target,
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arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits);
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bitmap_xor (cpu_isa, cpu_isa, target->isa);
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/* Ignore any bits that are quirk bits. */
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bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits);
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/* Ignore (for now) any bits that might be set by -mfpu. */
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bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits);
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@ -3263,6 +3266,10 @@ static void
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arm_option_override (void)
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{
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static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit };
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static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
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isa_quirkbits = sbitmap_alloc (isa_num_bits);
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arm_initialize_isa (isa_quirkbits, quirk_bitlist);
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isa_fpubits = sbitmap_alloc (isa_num_bits);
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arm_initialize_isa (isa_fpubits, fpu_bitlist);
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@ -3510,7 +3517,7 @@ arm_option_override (void)
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/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
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if (fix_cm3_ldrd == 2)
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{
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if (arm_selected_cpu->core == TARGET_CPU_cortexm3)
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if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd))
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fix_cm3_ldrd = 1;
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else
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fix_cm3_ldrd = 0;
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