re PR go/59432 (sync/atomic FAILs on 32bit x86 systems without .cfi directives)
PR go/59432 * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): Remove the second alternative. (regprefix): Remove mode attribute. (atomic_compare_and_swap<mode>): Do not fixup operand 2. * config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Remove. Revert: 2013-11-05 Ian Lance Taylor <iant@google.com> * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): If possible, add .cfi directives to record change to bx. * config/i386/i386.c (ix86_emit_cfi): New function. * config/i386/i386-protos.h (ix86_emit_cfi): Declare. From-SVN: r216281
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Uros Bizjak
Uros Bizjak
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1a1db0704b
@ -1,3 +1,20 @@
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2014-10-15 Uros Bizjak <ubizjak@gmail.com>
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PR go/59432
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* config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword):
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Remove the second alternative.
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(regprefix): Remove mode attribute.
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(atomic_compare_and_swap<mode>): Do not fixup operand 2.
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* config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Remove.
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Revert:
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2013-11-05 Ian Lance Taylor <iant@google.com>
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* config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword):
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If possible, add .cfi directives to record change to bx.
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* config/i386/i386.c (ix86_emit_cfi): New function.
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* config/i386/i386-protos.h (ix86_emit_cfi): Declare.
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2014-10-15 Jan Hubicka <hubicka@ucw.cz>
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PR lto/62026
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@ -142,7 +142,6 @@ extern void ix86_split_lshr (rtx *, rtx, enum machine_mode);
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extern rtx ix86_find_base_term (rtx);
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extern bool ix86_check_movabs (rtx, int);
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extern void ix86_split_idivmod (enum machine_mode, rtx[], bool);
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extern bool ix86_emit_cfi ();
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extern rtx assign_386_stack_local (enum machine_mode, enum ix86_stack_slot);
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extern int ix86_attr_length_immediate_default (rtx_insn *, bool);
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@ -17778,14 +17778,6 @@ ix86_split_idivmod (enum machine_mode mode, rtx operands[],
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emit_label (end_label);
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}
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/* Whether it is OK to emit CFI directives when emitting asm code. */
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bool
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ix86_emit_cfi ()
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{
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return dwarf2out_do_cfi_asm ();
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}
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#define LEA_MAX_STALL (3)
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#define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
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@ -1101,43 +1101,6 @@
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return parts.disp != NULL_RTX;
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})
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;; Return true if OP is memory operand which will need zero or
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;; one register at most, not counting stack pointer or frame pointer.
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(define_predicate "cmpxchg8b_pic_memory_operand"
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(match_operand 0 "memory_operand")
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{
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struct ix86_address parts;
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int ok;
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if (TARGET_64BIT || !flag_pic)
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return true;
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ok = ix86_decompose_address (XEXP (op, 0), &parts);
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gcc_assert (ok);
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if (parts.base && GET_CODE (parts.base) == SUBREG)
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parts.base = SUBREG_REG (parts.base);
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if (parts.index && GET_CODE (parts.index) == SUBREG)
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parts.index = SUBREG_REG (parts.index);
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if (parts.base == NULL_RTX
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|| parts.base == arg_pointer_rtx
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|| parts.base == frame_pointer_rtx
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|| parts.base == hard_frame_pointer_rtx
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|| parts.base == stack_pointer_rtx)
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return true;
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if (parts.index == NULL_RTX
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|| parts.index == arg_pointer_rtx
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|| parts.index == frame_pointer_rtx
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|| parts.index == hard_frame_pointer_rtx
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|| parts.index == stack_pointer_rtx)
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return true;
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return false;
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})
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;; Return true if OP is memory operand that cannot be represented
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;; by the modRM array.
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(define_predicate "long_memory_operand"
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@ -351,10 +351,9 @@
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else
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{
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enum machine_mode hmode = <CASHMODE>mode;
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rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n, mem;
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rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n;
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lo_o = operands[1];
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mem = operands[2];
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lo_e = operands[3];
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lo_n = operands[4];
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hi_o = gen_highpart (hmode, lo_o);
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@ -364,12 +363,9 @@
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lo_e = gen_lowpart (hmode, lo_e);
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lo_n = gen_lowpart (hmode, lo_n);
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if (!cmpxchg8b_pic_memory_operand (mem, <MODE>mode))
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mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
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emit_insn
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(gen_atomic_compare_and_swap<mode>_doubleword
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(lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n, operands[6]));
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(lo_o, hi_o, operands[2], lo_e, hi_e, lo_n, hi_n, operands[6]));
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}
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ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG),
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@ -398,56 +394,26 @@
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;; That said, in order to take advantage of possible lower-subreg opts,
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;; treat all of the integral operands in the same way.
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;; Operands 5 and 6 really need to be different registers, which in
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;; this case means op5 must not be ecx. If op5 and op6 are the same
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;; (like when the input is -1LL) GCC might chose to allocate op5 to ecx,
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;; like op6. This breaks, as the xchg will move the PIC register
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;; contents to %ecx then --> boom.
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(define_mode_attr doublemodesuffix [(SI "8") (DI "16")])
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(define_mode_attr regprefix [(SI "e") (DI "r")])
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(define_insn "atomic_compare_and_swap<dwi>_doubleword"
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[(set (match_operand:DWIH 0 "register_operand" "=a,a")
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[(set (match_operand:DWIH 0 "register_operand" "=a")
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(unspec_volatile:DWIH
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[(match_operand:<DWI> 2 "cmpxchg8b_pic_memory_operand" "+m,m")
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(match_operand:DWIH 3 "register_operand" "0,0")
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(match_operand:DWIH 4 "register_operand" "1,1")
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(match_operand:DWIH 5 "register_operand" "b,!*r")
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(match_operand:DWIH 6 "register_operand" "c,c")
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[(match_operand:<DWI> 2 "memory_operand" "+m")
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(match_operand:DWIH 3 "register_operand" "0")
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(match_operand:DWIH 4 "register_operand" "1")
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(match_operand:DWIH 5 "register_operand" "b")
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(match_operand:DWIH 6 "register_operand" "c")
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(match_operand:SI 7 "const_int_operand")]
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UNSPECV_CMPXCHG))
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(set (match_operand:DWIH 1 "register_operand" "=d,d")
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(set (match_operand:DWIH 1 "register_operand" "=d")
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(unspec_volatile:DWIH [(const_int 0)] UNSPECV_CMPXCHG))
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(set (match_dup 2)
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(unspec_volatile:<DWI> [(const_int 0)] UNSPECV_CMPXCHG))
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(set (reg:CCZ FLAGS_REG)
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(unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))
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(clobber (match_scratch:DWIH 8 "=X,&5"))]
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(unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))]
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"TARGET_CMPXCHG<doublemodesuffix>B"
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{
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bool swap = REGNO (operands[5]) != BX_REG;
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const char *xchg = "xchg{<imodesuffix>}\t%%<regprefix>bx, %5";
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if (swap)
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{
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output_asm_insn (xchg, operands);
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if (ix86_emit_cfi ())
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{
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output_asm_insn (".cfi_remember_state", operands);
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output_asm_insn (".cfi_register\t%%<regprefix>bx, %5", operands);
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}
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}
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output_asm_insn ("lock{%;} %K7cmpxchg<doublemodesuffix>b\t%2", operands);
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if (swap)
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{
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output_asm_insn (xchg, operands);
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if (ix86_emit_cfi ())
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output_asm_insn (".cfi_restore_state", operands);
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}
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return "";
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})
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"lock{%;} %K7cmpxchg<doublemodesuffix>b\t%2")
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;; For operand 2 nonmemory_operand predicate is used instead of
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;; register_operand to allow combiner to better optimize atomic
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