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Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.

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gcc/ChangeLog:

	* config/mips/mips.c (mips_ira_change_pseudo_allocno_class): New
	function.
	(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define macro.

gcc/testsuite/ChangeLog:

	* gcc.target/mips/pr65862-1.c: New test.
	* gcc.target/mips/pr65862-2.c: Likewise.

From-SVN: r224549
This commit is contained in:
Robert Suchanek 2015-06-17 09:55:59 +00:00 committed by Robert Suchanek
parent 7adcc56b9a
commit 1a4115ae75
5 changed files with 87 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2015-06-17 Robert Suchanek <robert.suchanek@imgtec.com>
* config/mips/mips.c (mips_ira_change_pseudo_allocno_class): New
function.
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define macro.
2015-06-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/66251

29
gcc/config/mips/mips.c
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@ -19402,6 +19402,33 @@ mips_lra_p (void)
{
return mips_lra_flag;
}
/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
static reg_class_t
mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class)
{
/* LRA will allocate an FPR for an integer mode pseudo instead of spilling
to memory if an FPR is present in the allocno class. It is rare that
we actually need to place an integer mode value in an FPR so where
possible limit the allocation to GR_REGS. This will slightly pessimize
code that involves integer to/from float conversions as these will have
to reload into FPRs in LRA. Such reloads are sometimes eliminated and
sometimes only partially eliminated. We choose to take this penalty
in order to eliminate usage of FPRs in code that does not use floating
point data.
This change has a similar effect to increasing the cost of FPR->GPR
register moves for integer modes so that they are higher than the cost
of memory but changing the allocno class is more reliable.
This is also similar to forbidding integer mode values in FPRs entirely
but this would lead to an inconsistency in the integer to/from float
instructions that say integer mode values must be placed in FPRs. */
if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS)
return GR_REGS;
return allocno_class;
}
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
@ -19658,6 +19685,8 @@ mips_lra_p (void)
#define TARGET_SPILL_CLASS mips_spill_class
#undef TARGET_LRA_P
#define TARGET_LRA_P mips_lra_p
#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
struct gcc_target targetm = TARGET_INITIALIZER;

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2015-06-17 Robert Suchanek <robert.suchanek@imgtec.com>
* gcc.target/mips/pr65862-1.c: New test.
* gcc.target/mips/pr65862-2.c: Likewise.
2015-06-17 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/pr54592.c: Remove dg-require-effective-target.

16
gcc/testsuite/gcc.target/mips/pr65862-1.c Normal file
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@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-not "\\\$f\[0-9\]+" } } */
int a, c;
int *b, *d;
void
fn1(int p1, int *p2(void *, void *), void *p3(void *, void *, int)) {
int n = c;
for (;;) {
a = 1;
for (; a < n;) {
*d = p1 && p2(0, (int *) ((long)p1 + 1));
p3(0, b + p1, 0);
}
}
}

31
gcc/testsuite/gcc.target/mips/pr65862-2.c Normal file
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@ -0,0 +1,31 @@
/* { dg-do compile } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-not "\\\$f\[0-9\]+" } } */
int a, b, d, e, j, k, n, o;
unsigned c, h, i, l, m, p;
int *f;
int *g;
int fn1(int p1) { return p1 - a; }
int fn2() {
b = b + 1 - a;
e = 1 + o + 1518500249;
d = d + n;
c = (int)c + g[0];
b = b + m + 1;
d = d + p + 1518500249;
d = d + k - 1;
c = fn1(c + j + 1518500249);
e = fn1(e + i + 1);
d = d + h + 1859775393 - a;
c = fn1(c + (d ^ 1 ^ b) + g[1] + 1);
b = fn1(b + m + 3);
d = fn1(d + l + 1);
b = b + (c ^ 1) + p + 1;
e = fn1(e + (b ^ c ^ d) + n + 1);
d = o;
b = 0;
e = e + k + 1859775393;
f[0] = e;
return a;
}