c-c++-common/gomp/pr60823-1.c: Change aarch64-*-* target to aarch64*-*-* target.
2018-01-22 Steve Ellcey <sellcey@marvell.com> c-c++-common/gomp/pr60823-1.c: Change aarch64-*-* target to aarch64*-*-* target. c-c++-common/gomp/pr60823-3.c: Ditto. g++.dg/gomp/declare-simd-1.C: Ditto. g++.dg/gomp/declare-simd-3.C: Ditto. g++.dg/gomp/declare-simd-4.C: Ditto. g++.dg/gomp/declare-simd-7.C: Ditto. g++.dg/gomp/pr88182.C: Ditto. gcc.dg/gomp/declare-simd-1.c: Ditto. gcc.dg/gomp/declare-simd-3.c: Ditto. gcc.dg/gomp/pr59669-2.c: Ditto. gcc.dg/gomp/pr87895-1.c: Ditto. gcc.dg/gomp/simd-clones-2.c: Ditto. gfortran.dg/gomp/declare-simd-2.f90: Ditto. gfortran.dg/gomp/pr79154-1.f90: Ditto. gfortran.dg/gomp/pr83977.f90: Ditto. From-SVN: r268168
This commit is contained in:
Steve Ellcey
Steve Ellcey
parent
c21af61d6d
commit
1b20e079b0
@ -1,3 +1,22 @@
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2018-01-22 Steve Ellcey <sellcey@marvell.com>
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c-c++-common/gomp/pr60823-1.c: Change aarch64-*-* target
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to aarch64*-*-* target.
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c-c++-common/gomp/pr60823-3.c: Ditto.
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g++.dg/gomp/declare-simd-1.C: Ditto.
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g++.dg/gomp/declare-simd-3.C: Ditto.
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g++.dg/gomp/declare-simd-4.C: Ditto.
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g++.dg/gomp/declare-simd-7.C: Ditto.
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g++.dg/gomp/pr88182.C: Ditto.
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gcc.dg/gomp/declare-simd-1.c: Ditto.
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gcc.dg/gomp/declare-simd-3.c: Ditto.
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gcc.dg/gomp/pr59669-2.c: Ditto.
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gcc.dg/gomp/pr87895-1.c: Ditto.
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gcc.dg/gomp/simd-clones-2.c: Ditto.
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gfortran.dg/gomp/declare-simd-2.f90: Ditto.
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gfortran.dg/gomp/pr79154-1.f90: Ditto.
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gfortran.dg/gomp/pr83977.f90: Ditto.
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2019-01-22 Jakub Jelinek <jakub@redhat.com>
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PR target/88965
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@ -17,4 +17,4 @@ foo (const double c1, const double c2)
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}
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return res;
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}
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-13 } */
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-13 } */
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@ -28,6 +28,6 @@ foo (double c1, double c2)
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baz (*(struct S *)&c1, *(struct S *)&c2);
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return c1 + c2 + ((struct S *)&c1)->c[1];
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}
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-16 } */
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-16 } */
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#endif
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@ -14,7 +14,7 @@ int f2 (int a, int *b, int c)
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return a + *b + c;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -90,8 +90,8 @@ namespace N1
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// { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
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struct A
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{
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@ -194,7 +194,7 @@ int B<int>::f25<7> (int a, int *b, int c)
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return a + *b + c;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -212,7 +212,7 @@ int B<int>::f26<-1> (int a, int *b, int c)
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return a + *b + c;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -244,7 +244,7 @@ f30 (int x)
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return x;
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}
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// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 }
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// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 }
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// { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -287,7 +287,7 @@ struct D
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int f37 (int a);
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int e;
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};
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// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-3 }
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// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-3 }
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void
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f38 (D &d)
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@ -13,7 +13,7 @@ int f1 (int a, int b, int c, int &d, int &e, int &f)
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return a + b + c + d + e + f;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-11 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
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// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -42,7 +42,7 @@ int f2 (int a, int b, int c, int &d, int &e, int &f)
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return a + b + c + d + e + f;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-17 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-17 }
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// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -58,7 +58,7 @@ int f3 (const int a, const int b, const int c, const int &d, const int &e, const
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return a + b + c + d + e + f;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -80,7 +80,7 @@ int f4 (const int a, const int b, const int c, const int &d, const int &e, const
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return a + b + c + d + e + f;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-11 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
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// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -5,7 +5,7 @@ f1 (int *p, int *q, short *s)
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return *p + *q + *s;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -22,7 +22,7 @@ f2 (int *p, short *q, int s, int r, int &t)
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return *p + *q + r;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -35,7 +35,7 @@ f3 (int &p, short &q, int s, int &r, int &t)
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return p + q + r;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
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// { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -18,7 +18,7 @@ foo1 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
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{
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return bar1 (a, b, c, d, e, f, g, h, i, j, k);
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
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#pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
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linear (f : 2) linear (ref (g) : 1) \
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@ -29,7 +29,7 @@ foo2 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
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{
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return bar2 (a, b, c, d, e, f, g, h, i, j, k);
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
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#pragma omp declare simd notinbranch uniform (b, c, d, e) aligned (e : 16) \
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linear (f : 2) linear (ref (g) : 1) \
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@ -40,7 +40,7 @@ foo3 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
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{
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return bar3 (a, b, c, d, e, f, g, h, i, j, k);
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
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#pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
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linear (f : 2) linear (ref (g) : 1) \
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@ -51,4 +51,4 @@ foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
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{
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return bar4 (a, b, c, d, e, f, g, h, i, j, k);
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
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@ -18,7 +18,7 @@ foo (double c1, double c2)
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}
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return res;
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}
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-15 }
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// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-15 }
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__attribute__((noinline, noclone)) void
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bar (double *x, double *y)
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@ -13,7 +13,7 @@ int f2 (int a, int *b, int c)
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return a + *b + c;
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}
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
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/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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@ -50,7 +50,7 @@ f7 (int x)
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return x;
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}
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/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64-*-* } .-7 } */
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/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 } */
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/* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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@ -70,7 +70,7 @@ f13 (int c; int *b; int a; int a, int *b, int c)
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return a + *b + c;
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}
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */
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/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
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/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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@ -89,7 +89,7 @@ f14 (a, b, c)
|
||||
return a + *b + c;
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-7 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
@ -106,7 +106,7 @@ f15 (int a, int *b, int c)
|
||||
return a + *b + c;
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
@ -128,7 +128,7 @@ int f17 (int g, long *h)
|
||||
return g + h[0];
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-5 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
@ -155,7 +155,7 @@ f18 (j, i)
|
||||
return j + i[0];
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64-*-* } .-7 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
|
||||
@ -5,7 +5,7 @@ f1 (int *p, int *q, short *s)
|
||||
return *p + *q + *s;
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
@ -22,7 +22,7 @@ f2 (int *p, short *q, int s, int r, int t)
|
||||
return *p + *q + r;
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
@ -7,4 +7,4 @@ void
|
||||
bar (int *a)
|
||||
{
|
||||
}
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-3 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-3 } */
|
||||
|
||||
@ -17,4 +17,4 @@ bar (int *x, int y)
|
||||
if ((y == 0) ? (*x = 0) : *x)
|
||||
return 0;
|
||||
}
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-5 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
|
||||
|
||||
@ -6,7 +6,7 @@ int addit(int a, int b, int *c)
|
||||
{
|
||||
return a + b;
|
||||
}
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-4 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 } */
|
||||
|
||||
#pragma omp declare simd uniform(a) aligned(a:32) linear(k:1) notinbranch
|
||||
float setArray(float *a, float x, int k)
|
||||
@ -15,7 +15,7 @@ float setArray(float *a, float x, int k)
|
||||
return a[k];
|
||||
}
|
||||
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } .-6 } */
|
||||
/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-6 } */
|
||||
/* { dg-final { scan-tree-dump "_ZGVbN4ua32vl_setArray" "optimized" { target i?86-*-* x86_64-*-* } } } */
|
||||
/* { dg-final { scan-tree-dump "_ZGVbN4vvva32_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
|
||||
/* { dg-final { scan-tree-dump "_ZGVbM4vl66u_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
! { dg-do compile }
|
||||
|
||||
function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } }
|
||||
function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
|
||||
integer, value :: a, b, c
|
||||
integer :: d, e, f, f1
|
||||
!$omp declare simd (f1) uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
|
||||
@ -12,7 +12,7 @@ function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mi
|
||||
f = f + 1
|
||||
f1 = a + b + c + d + e + f
|
||||
end function f1
|
||||
integer function f2 (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } }
|
||||
integer function f2 (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
|
||||
integer :: a, b
|
||||
!$omp declare simd uniform(b) linear(ref(a):b)
|
||||
a = a + 1
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
! PR fortran/79154
|
||||
! { dg-do compile }
|
||||
|
||||
pure real function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } }
|
||||
pure real function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
|
||||
!$omp declare simd(foo) ! { dg-bogus "may not appear in PURE or ELEMENTAL" }
|
||||
real, intent(in) :: a, b
|
||||
foo = a + b
|
||||
@ -20,7 +20,7 @@ pure real function baz (a, b)
|
||||
real, intent(in) :: a, b
|
||||
baz = a + b
|
||||
end function baz
|
||||
elemental real function fooe (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } }
|
||||
elemental real function fooe (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
|
||||
!$omp declare simd(fooe) ! { dg-bogus "may not appear in PURE or ELEMENTAL" }
|
||||
real, intent(in) :: a, b
|
||||
fooe = a + b
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
! PR middle-end/83977
|
||||
! { dg-do compile }
|
||||
|
||||
integer function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64-*-* } }
|
||||
integer function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
|
||||
integer :: a, b
|
||||
!$omp declare simd uniform(b) linear(ref(a):b)
|
||||
a = a + 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user