[AArch64] Fix PR87511
As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p should be evaluated as a HOST_WIDE_INT rather than int. Passes bootstrap & regress. gcc/ PR target/87511 * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p): Use HOST_WIDE_INT_1U for shift. testsuite/ PR target/87511 * gcc.target/aarch64/pr87511.c: Add new test. From-SVN: r265058
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2018-10-11 Wilco Dijkstra <wdijkstr@arm.com>
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PR target/87511
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* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
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Use HOST_WIDE_INT_1U for shift.
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2018-10-11 Doug Rupp <rupp@adacore.com>
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Olivier Hainque <hainque@adacore.com>
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@ -8842,7 +8842,8 @@ aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode mode, rtx mask,
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return CONST_INT_P (mask) && CONST_INT_P (shft_amnt)
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&& INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode)
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&& exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0
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&& (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;
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&& (INTVAL (mask)
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& ((HOST_WIDE_INT_1U << INTVAL (shft_amnt)) - 1)) == 0;
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}
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/* Calculate the cost of calculating X, storing it in *COST. Result
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@ -1,3 +1,8 @@
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2018-10-11 Wilco Dijkstra <wdijkstr@arm.com>
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PR target/87511
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* gcc.target/aarch64/pr87511.c: Add new test.
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2018-10-11 David Malcolm <dmalcolm@redhat.com>
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PR c++/84993
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16
gcc/testsuite/gcc.target/aarch64/pr87511.c
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gcc/testsuite/gcc.target/aarch64/pr87511.c
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/* { dg-do assemble } */
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/* { dg-options "-Os" } */
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int a, d;
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struct {
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signed f5 : 26;
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signed f6 : 12;
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} b;
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signed char c;
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void fn1() {
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signed char *e = &c;
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d = a * 10;
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*e = d;
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b.f6 = c;
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b.f5 = 8 <= 3;
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}
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