From 1b946b27649d6b8c0fcd4f6fdad9ff14dda1ffff Mon Sep 17 00:00:00 2001
From: "David S. Miller" <davem@davemloft.net>
Date: Mon, 26 Sep 2011 21:09:06 +0000
Subject: [PATCH] Add rdgsr, edge, and pixel-compare VIS tests.

gcc/testsuite/

	* gcc.target/sparc/rdgsr.c: New test.
	* gcc.target/sparc/edge.c: New test.
	* gcc.target/sparc/fcmp.c: New test.

From-SVN: r179215
---
 gcc/testsuite/ChangeLog                |  3 ++
 gcc/testsuite/gcc.target/sparc/edge.c  | 39 +++++++++++++++++++
 gcc/testsuite/gcc.target/sparc/fcmp.c  | 53 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/sparc/rdgsr.c |  9 +++++
 4 files changed, 104 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/sparc/edge.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/fcmp.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/rdgsr.c

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c8619b89f47..14476085743 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,6 +1,9 @@
 2011-09-26  David S. Miller  <davem@davemloft.net>
 
 	* gcc.target/sparc/wrgsr.c: New test.
+	* gcc.target/sparc/rdgsr.c: New test.
+	* gcc.target/sparc/edge.c: New test.
+	* gcc.target/sparc/fcmp.c: New test.
 
 2011-09-26  Janus Weil  <janus@gcc.gnu.org>
 
diff --git a/gcc/testsuite/gcc.target/sparc/edge.c b/gcc/testsuite/gcc.target/sparc/edge.c
new file mode 100644
index 00000000000..fcd7104d7d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/edge.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+
+int test_edge8 (void *p1, void *p2)
+{
+  return __builtin_vis_edge8 (p1, p2);
+}
+
+int test_edge8l (void *p1, void *p2)
+{
+  return __builtin_vis_edge8l (p1, p2);
+}
+
+int test_edge16 (void *p1, void *p2)
+{
+  return __builtin_vis_edge16 (p1, p2);
+}
+
+int test_edge16l (void *p1, void *p2)
+{
+  return __builtin_vis_edge16l (p1, p2);
+}
+
+int test_edge32 (void *p1, void *p2)
+{
+  return __builtin_vis_edge32 (p1, p2);
+}
+
+int test_edge32l (void *p1, void *p2)
+{
+  return __builtin_vis_edge32l (p1, p2);
+}
+
+/* { dg-final { scan-assembler "edge8\t%" } } */
+/* { dg-final { scan-assembler "edge8l\t%" } } */
+/* { dg-final { scan-assembler "edge16\t%" } } */
+/* { dg-final { scan-assembler "edge16l\t%" } } */
+/* { dg-final { scan-assembler "edge32\t%" } } */
+/* { dg-final { scan-assembler "edge32l\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc/testsuite/gcc.target/sparc/fcmp.c
new file mode 100644
index 00000000000..42b5bdcad3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fcmp.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+
+int test_fcmple16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmple16 (a, b);
+}
+
+int test_fcmple32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmple32 (a, b);
+}
+
+int test_fcmpne16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpne16 (a, b);
+}
+
+int test_fcmpne32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpne32 (a, b);
+}
+
+int test_fcmpgt16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpgt16 (a, b);
+}
+
+int test_fcmpgt32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpgt32 (a, b);
+}
+
+int test_fcmpeq16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpeq16 (a, b);
+}
+
+int test_fcmpeq32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpeq32 (a, b);
+}
+
+/* { dg-final { scan-assembler "fcmple16\t%" } } */
+/* { dg-final { scan-assembler "fcmple32\t%" } } */
+/* { dg-final { scan-assembler "fcmpne16\t%" } } */
+/* { dg-final { scan-assembler "fcmpne32\t%" } } */
+/* { dg-final { scan-assembler "fcmpgt16\t%" } } */
+/* { dg-final { scan-assembler "fcmpgt32\t%" } } */
+/* { dg-final { scan-assembler "fcmpeq16\t%" } } */
+/* { dg-final { scan-assembler "fcmpeq32\t%" } } */
diff --git a/gcc/testsuite/gcc.target/sparc/rdgsr.c b/gcc/testsuite/gcc.target/sparc/rdgsr.c
new file mode 100644
index 00000000000..e67bdaccded
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/rdgsr.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+
+long get_gsr (void)
+{
+	return __builtin_vis_read_gsr ();
+}
+
+/* { dg-final { scan-assembler "rd\t%gsr" } } */