aarch64: eliminate redundant zero extend after bitwise negation

The attached patch eliminates a redundant zero extend from the AArch64 backend. Given the following C code:

unsigned long long foo(unsigned a)
{
    return ~a;
}

prior to this patch, AArch64 GCC at -O2 generates:

foo:
        mvn     w0, w0
        uxtw    x0, w0
        ret

but the uxtw is redundant, since the mvn clears the upper half of the x0 register. After applying this patch, GCC at -O2 gives:

foo:
        mvn     w0, w0
        ret

Testing:
    Added regression test which passes after applying the change to aarch64.md.
    Full bootstrap and regression on aarch64-linux with no additional failures.

        * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
        * gcc.target/aarch64/mvn_zero_ext.c: New test.

gcc/ChangeLog

@@ -1,3 +1,7 @@
+2020-05-05  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
+
 2020-05-05  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/94800

gcc/config/aarch64/aarch64.md

@@ -4619,6 +4619,15 @@
    (set_attr "arch" "*,simd")]
 )
 
+(define_insn "*one_cmpl_zero_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (zero_extend:DI
+          (not:SI (match_operand:SI 1 "register_operand" "r"))))]
+  ""
+  "mvn\\t%w0, %w1"
+  [(set_attr "type" "logic_reg")]
+)
+
 (define_insn "*one_cmpl_<optab><mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 	(not:GPI (SHIFT:GPI (match_operand:GPI 1 "register_operand" "r")

gcc/testsuite/ChangeLog

@@ -1,3 +1,7 @@
+2020-05-05  Alex Coplan  <alex.coplan@arm.com>
+
+	* gcc.target/aarch64/mvn_zero_ext.c: New test.
+
 2020-05-05  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/94800

gcc/testsuite/gcc.target/aarch64/mvn_zero_ext.c

@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/*
+** foo:
+**	mvn	w0, w0
+**	ret
+*/
+unsigned long long
+foo (unsigned a)
+{
+  return ~a;
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */