sh.h (ROUND_TYPE_ALIGN, [...]): Complex modes are aligned like integral modes.
* sh.h (ROUND_TYPE_ALIGN, LOCAL_ALIGNMENT): Complex modes are aligned like integral modes. (SH5_WOULD_BE_PARTIAL_NREGS): Also test for CDImode and DCmode. * sh.h (EXTRA_CONSTRAINT_Csy): Allow PIC_DIRECT_ADDR_P. (LEGITIMATE_PIC_OPERAND_P): Allow LABEL_REF. * sh.md (*pt): Remove. * sh.h (REG_ALLOC_ORDER): Avoid squandering call-saved registers. * sh.md (return_media_rte): New pattern. (return_media): Use it. From-SVN: r68100
This commit is contained in:
J"orn Rennecke
Joern Rennecke
parent
71c6b99414
commit
1bf93c1483
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@ -1,3 +1,18 @@
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2003-06-17 J"orn Rennecke <joern.rennecke@superh.com>
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* sh.h (ROUND_TYPE_ALIGN, LOCAL_ALIGNMENT): Complex modes
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are aligned like integral modes.
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(SH5_WOULD_BE_PARTIAL_NREGS): Also test for CDImode and DCmode.
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* sh.h (EXTRA_CONSTRAINT_Csy): Allow PIC_DIRECT_ADDR_P.
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(LEGITIMATE_PIC_OPERAND_P): Allow LABEL_REF.
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* sh.md (*pt): Remove.
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* sh.h (REG_ALLOC_ORDER): Avoid squandering call-saved registers.
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* sh.md (return_media_rte): New pattern.
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(return_media): Use it.
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2003-06-17 Kazu Hirata <kazu@cs.umass.edu>
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* doc/contrib.texi: Replace Hitachi with Renesas.
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@ -619,6 +619,23 @@ do { \
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&& (ALIGN) < FASTEST_ALIGNMENT) \
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? FASTEST_ALIGNMENT : (ALIGN))
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/* get_mode_alignment assumes complex values are always held in multiple
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registers, but that is not the case on the SH; CQImode and CHImode are
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held in a single integer register. SH5 also holds CSImode and SCmode
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values in integer regsters. Thus the alignment needs to be bumped up
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to match the size of the mode. */
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#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
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(MAX ((GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_INT \
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|| GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_FLOAT) \
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? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (STRUCT))) \
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: (COMPUTED), \
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(SPECIFIED)))
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#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
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((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
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|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
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? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
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: ALIGN)
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/* Make arrays of chars word-aligned for the same reasons. */
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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(TREE_CODE (TYPE) == ARRAY_TYPE \
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@ -1264,26 +1281,35 @@ extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
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and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
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spilled or used otherwise, we better have the FP_REGS allocated first. */
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#define REG_ALLOC_ORDER \
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{ 65, 66, 67, 68, 69, 70, 71, 64, \
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72, 73, 74, 75, 76, 77, 78, 79, \
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136,137,138,139,140,141,142,143, \
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80, 81, 82, 83, 84, 85, 86, 87, \
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88, 89, 90, 91, 92, 93, 94, 95, \
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96, 97, 98, 99,100,101,102,103, \
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{/* Caller-saved FPRs */ \
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65, 66, 67, 68, 69, 70, 71, 64, \
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72, 73, 74, 75, 80, 81, 82, 83, \
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84, 85, 86, 87, 88, 89, 90, 91, \
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92, 93, 94, 95, 96, 97, 98, 99, \
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/* Callee-saved FPRs */ \
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76, 77, 78, 79,100,101,102,103, \
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104,105,106,107,108,109,110,111, \
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112,113,114,115,116,117,118,119, \
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120,121,122,123,124,125,126,127, \
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151, 1, 2, 3, 7, 6, 5, 4, \
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0, 8, 9, 10, 11, 12, 13, 14, \
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16, 17, 18, 19, 20, 21, 22, 23, \
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24, 25, 26, 27, 28, 29, 30, 31, \
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32, 33, 34, 35, 36, 37, 38, 39, \
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40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, \
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150, 15,145,146,147,144,148,149, \
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136,137,138,139,140,141,142,143, \
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/* FPSCR */ 151, \
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/* Caller-saved GPRs (except 8/9 on SH1-4) */ \
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1, 2, 3, 7, 6, 5, 4, 0, \
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8, 9, 17, 19, 20, 21, 22, 23, \
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36, 37, 38, 39, 40, 41, 42, 43, \
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60, 61, 62, \
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/* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
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10, 11, 12, 13, 14, 18, \
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/* SH5 callee-saved GPRs */ \
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28, 29, 30, 31, 32, 33, 34, 35, \
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44, 45, 46, 47, 48, 49, 50, 51, \
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52, 53, 54, 55, 56, 57, 58, 59, \
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/* FPUL */ 150, \
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/* SH5 branch target registers */ \
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128,129,130,131,132,133,134,135, \
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152 }
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/* Fixed registers */ \
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15, 16, 24, 25, 26, 27, 63,144, \
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145,146,147,148,149,152 }
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/* The class value for index registers, and the one for base regs. */
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#define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
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@ -2158,7 +2184,9 @@ do { \
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: 0)
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#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
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(TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \
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(TARGET_SH5 \
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&& ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
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|| (MODE) == DCmode) \
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&& ((CUM).arg_count[(int) SH_ARG_INT] \
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+ (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
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@ -2462,7 +2490,7 @@ while (0)
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/* The `Csy' constraint is a label or a symbol. */
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#define EXTRA_CONSTRAINT_Csy(OP) \
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(NON_PIC_REFERENCE_P (OP))
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(NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
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/* A zero in any shape or form. */
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#define EXTRA_CONSTRAINT_Z(OP) \
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@ -2889,10 +2917,11 @@ while (0)
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/* We can't directly access anything that contains a symbol,
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nor can we indirect via the constant pool. */
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#define LEGITIMATE_PIC_OPERAND_P(X) \
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(! nonpic_symbol_mentioned_p (X) \
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&& (GET_CODE (X) != SYMBOL_REF \
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|| ! CONSTANT_POOL_ADDRESS_P (X) \
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|| ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
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((! nonpic_symbol_mentioned_p (X) \
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&& (GET_CODE (X) != SYMBOL_REF \
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|| ! CONSTANT_POOL_ADDRESS_P (X) \
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|| ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
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|| (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
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#define SYMBOLIC_CONST_P(X) \
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((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
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@ -6637,19 +6637,6 @@
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}
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")
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;; When generating PIC, we must match label_refs especially, because
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;; they do not satisfy LEGITIMATE_PIC_OPERAND_P(), and we don't want
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;; them to do, because they can't be loaded directly into
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;; non-branch-target registers.
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(define_insn "*pt"
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[(set (match_operand:DI 0 "target_reg_operand" "=b")
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(match_operand:DI 1 "" "Csy"))]
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"TARGET_SHMEDIA && flag_pic
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&& EXTRA_CONSTRAINT_Csy (operands[1])"
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"pt %1, %0"
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[(set_attr "type" "pt_media")
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(set_attr "length" "*")])
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(define_insn "*ptb"
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[(set (match_operand:DI 0 "target_reg_operand" "=b")
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(const:DI (unspec:DI [(match_operand:DI 1 "" "Csy")]
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@ -7237,6 +7224,12 @@ mov.l\\t1f,r0\\n\\
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"blink %0, r63"
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[(set_attr "type" "jump_media")])
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(define_insn "return_media_rte"
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[(return)]
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"TARGET_SHMEDIA && reload_completed && current_function_interrupt"
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"rte"
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[(set_attr "type" "jump_media")])
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(define_expand "return_media"
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[(return)]
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"TARGET_SHMEDIA && reload_completed"
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@ -7245,6 +7238,11 @@ mov.l\\t1f,r0\\n\\
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int tr_regno = sh_media_register_for_return ();
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rtx tr;
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if (current_function_interrupt)
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{
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emit_jump_insn (gen_return_media_rte ());
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DONE;
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}
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if (tr_regno < 0)
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{
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rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
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