Jakub Jelinek <jj@ultra.linux.cz>
* config/sparc/sparc.h (ASM_DECLARE_REGISTER_GLOBAL): New macro.
(RTX_OK_FOR_OLO10): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): If assembler supports offsetable
%lo(), allow it in addresses...
(PRINT_OPERAND_ADDRESS): ... and print it appropriately.
* config/sparc/sparc.md (sethi_di_medlow_embmedany_pic): sethi %lo()
does not make sense.
* config/sparc/sparc.c (sparc_hard_reg_printed): New array.
(sparc_output_scratch_registers): New function.
(output_function_prologue, sparc_flat_output_function_prologue): Use
it.
* varasm.c (make_decl_rtl): Use ASM_DECLARE_REGISTER_GLOBAL if
defined.
* tm.texi (ASM_DECLARE_REGISTER_GLOBAL): Document it.
* configure.in: Add check for .register pseudo-op support in as and
check for offsetable %lo().
* acconfig.h: Add templates for the above checks.
* configure: Regenerate.
Richard Henderson <rth@cygnus.com>
* sparc/linux64.h (TARGET_DEFAULT): Remove MASK_APP_REGS.
* sparc/sol2-sld-64.h (TARGET_DEFAULT): Likewise.
* sparc/sol2.h (TARGET_DEFAULT): Likewise.
From-SVN: r28414
This commit is contained in:
Richard Henderson
parent
e76d23764b
commit
1cb36a981d
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@ -1,3 +1,30 @@
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1999-08-02 Jakub Jelinek <jj@ultra.linux.cz>
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* config/sparc/sparc.h (ASM_DECLARE_REGISTER_GLOBAL): New macro.
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(RTX_OK_FOR_OLO10): Likewise.
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(GO_IF_LEGITIMATE_ADDRESS): If assembler supports offsetable
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%lo(), allow it in addresses...
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(PRINT_OPERAND_ADDRESS): ... and print it appropriately.
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* config/sparc/sparc.md (sethi_di_medlow_embmedany_pic): sethi %lo()
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does not make sense.
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* config/sparc/sparc.c (sparc_hard_reg_printed): New array.
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(sparc_output_scratch_registers): New function.
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(output_function_prologue, sparc_flat_output_function_prologue): Use
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it.
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* varasm.c (make_decl_rtl): Use ASM_DECLARE_REGISTER_GLOBAL if
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defined.
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* tm.texi (ASM_DECLARE_REGISTER_GLOBAL): Document it.
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* configure.in: Add check for .register pseudo-op support in as and
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check for offsetable %lo().
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* acconfig.h: Add templates for the above checks.
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* configure: Regenerate.
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1999-08-02 Richard Henderson <rth@cygnus.com>
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* sparc/linux64.h (TARGET_DEFAULT): Remove MASK_APP_REGS.
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* sparc/sol2-sld-64.h (TARGET_DEFAULT): Likewise.
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* sparc/sol2.h (TARGET_DEFAULT): Likewise.
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Mon Aug 2 23:46:45 1999 J"orn Rennecke <amylaar@cygnus.co.uk>
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* loop.c (strength_reduce): When doing biv->giv conversion, fix up
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@ -29,6 +29,12 @@
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/* Define if your assembler supports .balign and .p2align. */
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#undef HAVE_GAS_BALIGN_AND_P2ALIGN
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/* Define if your assembler supports offsetable %lo(). */
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#undef HAVE_AS_OFFSETABLE_LO10
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/* Define if your assembler supports .register. */
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#undef HAVE_AS_REGISTER_PSEUDO_OP
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/* Define if your assembler supports .subsection and .subsection -1 starts
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emitting at the beginning of your section */
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#undef HAVE_GAS_SUBSECTION_ORDERING
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@ -41,7 +41,7 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
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+ MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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+ MASK_STACK_BIAS + MASK_EPILOGUE + MASK_FPU)
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#endif
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/* Output at beginning of assembler file. */
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@ -18,7 +18,7 @@
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
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MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
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MASK_STACK_BIAS + MASK_EPILOGUE + MASK_FPU)
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#endif
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/* The default code model. */
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@ -213,7 +213,7 @@ Boston, MA 02111-1307, USA. */
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/* Solaris allows 64 bit out and global registers in 32 bit mode.
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sparc_override_options will disable V8+ if not generating V9 code. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS)
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#define TARGET_DEFAULT (MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS)
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/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
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traps available which can get and set the condition codes
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@ -141,6 +141,8 @@ int sparc_align_loops;
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int sparc_align_jumps;
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int sparc_align_funcs;
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char sparc_hard_reg_printed[8];
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struct sparc_cpu_select sparc_select[] =
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{
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/* switch name, tune arch */
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@ -3108,6 +3110,32 @@ build_big_number (file, num, reg)
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}
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}
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/* Output any necessary .register pseudo-ops. */
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void
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sparc_output_scratch_registers (file)
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FILE *file;
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{
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#ifdef HAVE_AS_REGISTER_PSEUDO_OP
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int i;
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if (TARGET_ARCH32)
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return;
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/* Check if %g[2367] were used without
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.register being printed for them already. */
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for (i = 2; i < 8; i++)
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{
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if (regs_ever_live [i]
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&& ! sparc_hard_reg_printed [i])
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{
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sparc_hard_reg_printed [i] = 1;
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fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
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}
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if (i == 3) i = 5;
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}
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#endif
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}
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/* Output code for the function prologue. */
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void
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@ -3116,6 +3144,8 @@ output_function_prologue (file, size, leaf_function)
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int size;
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int leaf_function;
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{
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sparc_output_scratch_registers (file);
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/* Need to use actual_fsize, since we are also allocating
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space for our callee (and our own register save area). */
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actual_fsize = compute_frame_size (size, leaf_function);
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@ -5849,6 +5879,8 @@ sparc_flat_output_function_prologue (file, size)
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char *sp_str = reg_names[STACK_POINTER_REGNUM];
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unsigned long gmask = current_frame_info.gmask;
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sparc_output_scratch_registers (file);
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/* This is only for the human reader. */
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fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
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fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
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@ -1822,6 +1822,31 @@ do { \
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ASM_OUTPUT_LABEL (FILE, NAME); \
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} while (0)
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/* Output the special assembly code needed to tell the assembler some
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register is used as global register variable. */
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#ifdef HAVE_AS_REGISTER_PSEUDO_OP
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#define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
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do { \
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if (TARGET_ARCH64) \
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{ \
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int __end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
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int __reg; \
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extern char sparc_hard_reg_printed[8]; \
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for (__reg = (REGNO); __reg < 8 && __reg < __end; __reg++) \
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if ((__reg & ~1) == 2 || (__reg & ~1) == 6) \
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{ \
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if (__reg == (REGNO)) \
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fprintf ((FILE), "\t.register\t%%g%d, %s\n", __reg, (NAME)); \
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else \
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fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
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__reg, __reg - (REGNO), (NAME)); \
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sparc_hard_reg_printed[__reg] = 1; \
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} \
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} \
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} while (0)
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#endif
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/* This macro generates the assembly code for function entry.
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FILE is a stdio stream to output the code to.
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SIZE is an int: how many units of temporary storage to allocate.
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@ -2233,6 +2258,14 @@ extern struct rtx_def *sparc_builtin_saveregs ();
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: 0))
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#endif
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/* Should gcc use [%reg+%lo(xx)+offset] addresses? */
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#ifdef HAVE_AS_OFFSETABLE_LO10
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#define USE_AS_OFFSETABLE_LO10 1
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#else
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#define USE_AS_OFFSETABLE_LO10 0
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#endif
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/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
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that is a valid memory address for an instruction.
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The MODE argument is the machine mode for the MEM expression
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@ -2257,6 +2290,9 @@ extern struct rtx_def *sparc_builtin_saveregs ();
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#define RTX_OK_FOR_OFFSET_P(X) \
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(GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
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#define RTX_OK_FOR_OLO10_P(X) \
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(GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
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#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
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{ if (RTX_OK_FOR_BASE_P (X)) \
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@ -2308,6 +2344,30 @@ extern struct rtx_def *sparc_builtin_saveregs ();
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|| RTX_OK_FOR_OFFSET_P (op0)) \
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goto ADDR; \
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} \
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else if (USE_AS_OFFSETABLE_LO10 \
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&& GET_CODE (op0) == LO_SUM \
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&& TARGET_ARCH64 \
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&& ! TARGET_CM_MEDMID \
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&& RTX_OK_FOR_OLO10_P (op1)) \
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{ \
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register rtx op00 = XEXP (op0, 0); \
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register rtx op01 = XEXP (op0, 1); \
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if (RTX_OK_FOR_BASE_P (op00) \
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&& CONSTANT_P (op01)) \
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goto ADDR; \
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} \
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else if (USE_AS_OFFSETABLE_LO10 \
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&& GET_CODE (op1) == LO_SUM \
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&& TARGET_ARCH64 \
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&& ! TARGET_CM_MEDMID \
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&& RTX_OK_FOR_OLO10_P (op0)) \
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{ \
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register rtx op10 = XEXP (op1, 0); \
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register rtx op11 = XEXP (op1, 1); \
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if (RTX_OK_FOR_BASE_P (op10) \
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&& CONSTANT_P (op11)) \
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goto ADDR; \
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} \
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} \
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else if (GET_CODE (X) == LO_SUM) \
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{ \
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@ -3115,15 +3175,29 @@ do { \
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offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
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else \
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base = XEXP (addr, 0), index = XEXP (addr, 1); \
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fputs (reg_names[REGNO (base)], FILE); \
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if (index == 0) \
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fprintf (FILE, "%+d", offset); \
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else if (GET_CODE (index) == REG) \
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fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
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else if (GET_CODE (index) == SYMBOL_REF \
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|| GET_CODE (index) == CONST) \
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fputc ('+', FILE), output_addr_const (FILE, index); \
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else abort (); \
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if (GET_CODE (base) == LO_SUM) \
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{ \
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if (! USE_AS_OFFSETABLE_LO10 \
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|| TARGET_ARCH32 \
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|| TARGET_CM_MEDMID) \
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abort (); \
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output_operand (XEXP (base, 0), 0); \
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fputs ("+%lo(", FILE); \
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output_address (XEXP (base, 1)); \
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fprintf (FILE, ")+%d", offset); \
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} \
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else \
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{ \
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fputs (reg_names[REGNO (base)], FILE); \
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if (index == 0) \
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fprintf (FILE, "%+d", offset); \
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else if (GET_CODE (index) == REG) \
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fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
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else if (GET_CODE (index) == SYMBOL_REF \
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|| GET_CODE (index) == CONST) \
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fputc ('+', FILE), output_addr_const (FILE, index); \
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else abort (); \
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} \
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||||
} \
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else if (GET_CODE (addr) == MINUS \
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&& GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
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|
|
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@ -2495,7 +2495,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
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"(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
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"sethi\\t%%lo(%a1), %0"
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"sethi\\t%%hi(%a1), %0"
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||||
[(set_attr "type" "move")
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||||
(set_attr "length" "1")])
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||||
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||||
|
|
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|
@ -8325,10 +8325,62 @@ EOF
|
|||
fi
|
||||
echo "$ac_t""$gcc_cv_as_subsections" 1>&6
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||||
|
||||
echo $ac_n "checking assembler instructions""... $ac_c" 1>&6
|
||||
echo "configure:8330: checking assembler instructions" >&5
|
||||
gcc_cv_as_instructions=
|
||||
if test x$gcc_cv_as != x; then
|
||||
case "$target" in
|
||||
sparc*-*-*)
|
||||
echo $ac_n "checking assembler .register pseudo-op support""... $ac_c" 1>&6
|
||||
echo "configure:8332: checking assembler .register pseudo-op support" >&5
|
||||
gcc_cv_as_register_pseudo_op=
|
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if test x$gcc_cv_as != x; then
|
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# Check if we have .register
|
||||
echo ".register %g2, #scratch" > conftest.s
|
||||
if $gcc_cv_as -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_register_pseudo_op=yes
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||||
cat >> confdefs.h <<\EOF
|
||||
#define HAVE_AS_REGISTER_PSEUDO_OP 1
|
||||
EOF
|
||||
|
||||
fi
|
||||
rm -f conftest.s conftest.o
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||||
fi
|
||||
echo "$ac_t""$gcc_cv_as_register_pseudo_op" 1>&6
|
||||
|
||||
echo $ac_n "checking assembler offsetable %lo() support""... $ac_c" 1>&6
|
||||
echo "configure:8349: checking assembler offsetable %lo() support" >&5
|
||||
gcc_cv_as_offsetable_lo10=
|
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if test x$gcc_cv_as != x; then
|
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# Check if assembler has offsetable %lo()
|
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echo "or %g1, %lo(ab) + 12, %g1" > conftest.s
|
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echo "or %g1, %lo(ab + 12), %g1" > conftest1.s
|
||||
gcc_cv_as_flags64="-xarch=v9"
|
||||
if ! $gcc_cv_as $gcc_cv_as_flags64 -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_flags64="-64"
|
||||
if ! $gcc_cv_as $gcc_cv_as_flags64 -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_flags64=""
|
||||
fi
|
||||
fi
|
||||
if test -n "$gcc_cv_as_flags64" ; then
|
||||
if $gcc_cv_as $gcc_cv_as_flags64 -o conftest1.o conftest1.s > /dev/null 2>&1; then
|
||||
if cmp conftest.o conftest1.o > /dev/null 2>&1; then
|
||||
:
|
||||
else
|
||||
gcc_cv_as_offsetable_lo10=yes
|
||||
cat >> confdefs.h <<\EOF
|
||||
#define HAVE_AS_OFFSETABLE_LO10 1
|
||||
EOF
|
||||
|
||||
fi
|
||||
fi
|
||||
fi
|
||||
rm -f conftest.s conftest.o conftest1.s conftest1.o
|
||||
fi
|
||||
echo "$ac_t""$gcc_cv_as_offsetable_lo10" 1>&6
|
||||
;;
|
||||
|
||||
i[34567]86-*-*)
|
||||
echo $ac_n "checking assembler instructions""... $ac_c" 1>&6
|
||||
echo "configure:8382: checking assembler instructions" >&5
|
||||
gcc_cv_as_instructions=
|
||||
if test x$gcc_cv_as != x; then
|
||||
set "filds fists" "filds mem; fists mem"
|
||||
while test $# -gt 0
|
||||
do
|
||||
|
|
@ -8343,8 +8395,10 @@ EOF
|
|||
shift 2
|
||||
done
|
||||
rm -f conftest.s conftest.o
|
||||
fi
|
||||
echo "$ac_t""$gcc_cv_as_instructions" 1>&6
|
||||
fi
|
||||
echo "$ac_t""$gcc_cv_as_instructions" 1>&6
|
||||
;;
|
||||
esac
|
||||
|
||||
# Figure out what language subdirectories are present.
|
||||
# Look if the user specified --enable-languages="..."; if not, use
|
||||
|
|
|
|||
|
|
@ -4153,9 +4153,55 @@ EOF
|
|||
fi
|
||||
AC_MSG_RESULT($gcc_cv_as_subsections)
|
||||
|
||||
AC_MSG_CHECKING(assembler instructions)
|
||||
gcc_cv_as_instructions=
|
||||
if test x$gcc_cv_as != x; then
|
||||
case "$target" in
|
||||
sparc*-*-*)
|
||||
AC_MSG_CHECKING(assembler .register pseudo-op support)
|
||||
gcc_cv_as_register_pseudo_op=
|
||||
if test x$gcc_cv_as != x; then
|
||||
# Check if we have .register
|
||||
echo ".register %g2, #scratch" > conftest.s
|
||||
if $gcc_cv_as -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_register_pseudo_op=yes
|
||||
AC_DEFINE(HAVE_AS_REGISTER_PSEUDO_OP)
|
||||
fi
|
||||
rm -f conftest.s conftest.o
|
||||
fi
|
||||
AC_MSG_RESULT($gcc_cv_as_register_pseudo_op)
|
||||
|
||||
AC_MSG_CHECKING([assembler offsetable %lo() support])
|
||||
gcc_cv_as_offsetable_lo10=
|
||||
if test x$gcc_cv_as != x; then
|
||||
# Check if assembler has offsetable %lo()
|
||||
echo "or %g1, %lo(ab) + 12, %g1" > conftest.s
|
||||
echo "or %g1, %lo(ab + 12), %g1" > conftest1.s
|
||||
gcc_cv_as_flags64="-xarch=v9"
|
||||
if ! $gcc_cv_as $gcc_cv_as_flags64 -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_flags64="-64"
|
||||
if ! $gcc_cv_as $gcc_cv_as_flags64 -o conftest.o conftest.s > /dev/null 2>&1; then
|
||||
gcc_cv_as_flags64=""
|
||||
fi
|
||||
fi
|
||||
if test -n "$gcc_cv_as_flags64" ; then
|
||||
if $gcc_cv_as $gcc_cv_as_flags64 -o conftest1.o conftest1.s > /dev/null 2>&1; then
|
||||
if cmp conftest.o conftest1.o > /dev/null 2>&1; then
|
||||
:
|
||||
else
|
||||
gcc_cv_as_offsetable_lo10=yes
|
||||
AC_DEFINE(HAVE_AS_OFFSETABLE_LO10)
|
||||
fi
|
||||
fi
|
||||
fi
|
||||
rm -f conftest.s conftest.o conftest1.s conftest1.o
|
||||
fi
|
||||
AC_MSG_RESULT($gcc_cv_as_offsetable_lo10)
|
||||
;;
|
||||
|
||||
changequote(,)dnl
|
||||
i[34567]86-*-*)
|
||||
changequote([,])dnl
|
||||
AC_MSG_CHECKING(assembler instructions)
|
||||
gcc_cv_as_instructions=
|
||||
if test x$gcc_cv_as != x; then
|
||||
set "filds fists" "filds mem; fists mem"
|
||||
while test $# -gt 0
|
||||
do
|
||||
|
|
@ -4167,8 +4213,10 @@ if test x$gcc_cv_as != x; then
|
|||
shift 2
|
||||
done
|
||||
rm -f conftest.s conftest.o
|
||||
fi
|
||||
AC_MSG_RESULT($gcc_cv_as_instructions)
|
||||
fi
|
||||
AC_MSG_RESULT($gcc_cv_as_instructions)
|
||||
;;
|
||||
esac
|
||||
|
||||
# Figure out what language subdirectories are present.
|
||||
# Look if the user specified --enable-languages="..."; if not, use
|
||||
|
|
|
|||
|
|
@ -5591,6 +5591,15 @@ label definition (perhaps using @code{ASM_OUTPUT_LABEL}). The argument
|
|||
If this macro is not defined, then the variable name is defined in the
|
||||
usual manner as a label (by means of @code{ASM_OUTPUT_LABEL}).
|
||||
|
||||
@findex ASM_DECLARE_REGISTER_GLOBAL
|
||||
@item ASM_DECLARE_REGISTER_GLOBAL (@var{stream}, @var{decl}, @var{regno}, @var{name})
|
||||
A C statement (sans semicolon) to output to the stdio stream
|
||||
@var{stream} any text necessary for claiming a register @var{regno}
|
||||
for a global variable @var{decl} with name @var{name}.
|
||||
|
||||
If you don't define this macro, that is equivalent to defining it to do
|
||||
nothing.
|
||||
|
||||
@findex ASM_FINISH_DECLARE_OBJECT
|
||||
@item ASM_FINISH_DECLARE_OBJECT (@var{stream}, @var{decl}, @var{toplevel}, @var{atend})
|
||||
A C statement (sans semicolon) to finish up declaring a variable name
|
||||
|
|
|
|||
|
|
@ -704,6 +704,9 @@ make_decl_rtl (decl, asmspec, top_level)
|
|||
{
|
||||
/* Make this register global, so not usable for anything
|
||||
else. */
|
||||
#ifdef ASM_DECLARE_REGISTER_GLOBAL
|
||||
ASM_DECLARE_REGISTER_GLOBAL (asm_out_file, decl, reg_number, name);
|
||||
#endif
|
||||
nregs = HARD_REGNO_NREGS (reg_number, DECL_MODE (decl));
|
||||
while (nregs > 0)
|
||||
globalize_reg (reg_number + --nregs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue