Add floating point ld/st indexed patterns.
From-SVN: r3145
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@ -1225,6 +1225,26 @@
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[(set_attr "type" "fpalu,move,fpstore,store,fpload,load,fpload,load")
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(set_attr "length" "1,2,1,2,1,2,3,3")])
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=fx")
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(mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"flddx,s %1(0,%2),%0"
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[(set_attr "type" "fpload")
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(set_attr "length" "1")])
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(define_insn ""
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[(set (mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r")))
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(match_operand:DF 0 "register_operand" "fx"))]
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"! TARGET_DISABLE_INDEXING"
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"fstdx,s %0,%1(0,%2)"
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[(set_attr "type" "fpstore")
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(set_attr "length" "1")])
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(define_expand "movdi"
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[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
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(match_operand:DI 1 "general_operand" ""))]
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@ -1388,6 +1408,26 @@
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stw%M0 %r1,%0"
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[(set_attr "type" "fpalu,move,load,fpload,fpload,load,fpstore,store")
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(set_attr "length" "1,1,2,2,1,1,1,1")])
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=fx")
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(mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"fldwx,s %1(0,%2),%0"
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[(set_attr "type" "fpload")
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(set_attr "length" "1")])
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(define_insn ""
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[(set (mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r")))
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(match_operand:SF 0 "register_operand" "fx"))]
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"! TARGET_DISABLE_INDEXING"
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"fstwx,s %0,%1(0,%2)"
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[(set_attr "type" "fpstore")
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(set_attr "length" "1")])
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;;- zero extension instructions
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