From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES, BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40, BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU. (bfin_init_builtins): Initialize __builtin_bfin_ones, __builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16, __builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32, __builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub, __builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16. (bdesc_1arg): Add __builtin_bfin_ones. (bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40, and __builtin_bfin_csqu_fr16. * config/bfin/bfin.md (UNSPEC_ONES): New constant. (ones): New define_insn. (ssaddhi3_parts): New define_insn. (sssubhi3_parts): New define_insn. (flag_mulhi_parts): New define_insn. From-SVN: r128475
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
eae8e4741e
commit
1d7d5ac4e8
@ -1,3 +1,25 @@
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2007-09-13 Bernd Schmidt <bernd.schmidt@analog.com>
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From Jie Zhang:
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* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
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BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
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BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
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(bfin_init_builtins): Initialize __builtin_bfin_ones,
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__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
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__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
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__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
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__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
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__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
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(bdesc_1arg): Add __builtin_bfin_ones.
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(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
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__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
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and __builtin_bfin_csqu_fr16.
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* config/bfin/bfin.md (UNSPEC_ONES): New constant.
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(ones): New define_insn.
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(ssaddhi3_parts): New define_insn.
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(sssubhi3_parts): New define_insn.
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(flag_mulhi_parts): New define_insn.
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2007-09-13 Seongbae Park <seongbae.park@gmail.com>
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* common.opt (femit-class-debug-always): Turn off by default.
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@ -4881,6 +4881,7 @@ enum bfin_builtins
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{
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BFIN_BUILTIN_CSYNC,
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BFIN_BUILTIN_SSYNC,
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BFIN_BUILTIN_ONES,
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BFIN_BUILTIN_COMPOSE_2X16,
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BFIN_BUILTIN_EXTRACTLO,
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BFIN_BUILTIN_EXTRACTHI,
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@ -4937,6 +4938,12 @@ enum bfin_builtins
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BFIN_BUILTIN_CPLX_MAC_16,
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BFIN_BUILTIN_CPLX_MSU_16,
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BFIN_BUILTIN_CPLX_MUL_16_S40,
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BFIN_BUILTIN_CPLX_MAC_16_S40,
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BFIN_BUILTIN_CPLX_MSU_16_S40,
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BFIN_BUILTIN_CPLX_SQU,
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BFIN_BUILTIN_MAX
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};
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@ -4996,6 +5003,8 @@ bfin_init_builtins (void)
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def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC);
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def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC);
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def_builtin ("__builtin_bfin_ones", short_ftype_int, BFIN_BUILTIN_ONES);
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def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int,
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BFIN_BUILTIN_COMPOSE_2X16);
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def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi,
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@ -5025,6 +5034,11 @@ bfin_init_builtins (void)
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def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi,
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BFIN_BUILTIN_ABS_2X16);
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def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int,
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BFIN_BUILTIN_MIN_1X16);
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def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int,
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BFIN_BUILTIN_MAX_1X16);
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def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int,
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BFIN_BUILTIN_SSADD_1X16);
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def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int,
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@ -5056,6 +5070,11 @@ bfin_init_builtins (void)
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def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi,
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BFIN_BUILTIN_MULHISIHH);
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def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int,
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BFIN_BUILTIN_MIN_1X32);
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def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int,
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BFIN_BUILTIN_MAX_1X32);
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def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int,
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BFIN_BUILTIN_SSADD_1X32);
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def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int,
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@ -5088,12 +5107,24 @@ bfin_init_builtins (void)
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BFIN_BUILTIN_SSASHIFT_1X32);
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/* Complex numbers. */
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def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi,
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BFIN_BUILTIN_SSADD_2X16);
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def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi,
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BFIN_BUILTIN_SSSUB_2X16);
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def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MUL_16);
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def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MAC_16);
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def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MSU_16);
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def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MUL_16_S40);
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def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MAC_16_S40);
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def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi,
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BFIN_BUILTIN_CPLX_MSU_16_S40);
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def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi,
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BFIN_BUILTIN_CPLX_SQU);
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}
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@ -5141,6 +5172,8 @@ static const struct builtin_description bdesc_2arg[] =
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static const struct builtin_description bdesc_1arg[] =
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{
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{ CODE_FOR_ones, "__builtin_bfin_ones", BFIN_BUILTIN_ONES, 0 },
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{ CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 },
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{ CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 },
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{ CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 },
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@ -5381,6 +5414,7 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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return target;
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case BFIN_BUILTIN_CPLX_MUL_16:
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case BFIN_BUILTIN_CPLX_MUL_16_S40:
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arg0 = CALL_EXPR_ARG (exp, 0);
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arg1 = CALL_EXPR_ARG (exp, 1);
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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@ -5396,9 +5430,14 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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if (! register_operand (op1, GET_MODE (op1)))
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op1 = copy_to_mode_reg (GET_MODE (op1), op1);
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emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, GEN_INT (MACFLAG_NONE)));
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if (fcode == BFIN_BUILTIN_CPLX_MUL_16)
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emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, GEN_INT (MACFLAG_W32)));
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else
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emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, GEN_INT (MACFLAG_NONE)));
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emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx,
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const1_rtx, const1_rtx,
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const0_rtx, accvec, const1_rtx, const0_rtx,
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@ -5408,6 +5447,8 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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case BFIN_BUILTIN_CPLX_MAC_16:
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case BFIN_BUILTIN_CPLX_MSU_16:
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case BFIN_BUILTIN_CPLX_MAC_16_S40:
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case BFIN_BUILTIN_CPLX_MSU_16_S40:
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arg0 = CALL_EXPR_ARG (exp, 0);
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arg1 = CALL_EXPR_ARG (exp, 1);
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arg2 = CALL_EXPR_ARG (exp, 2);
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@ -5431,13 +5472,30 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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emit_move_insn (tmp2, gen_lowpart (SImode, op0));
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emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx));
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emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2));
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emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, accvec, const0_rtx,
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const0_rtx,
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GEN_INT (MACFLAG_W32)));
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tmp1 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const1_rtx : const0_rtx);
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tmp2 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const0_rtx : const1_rtx);
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if (fcode == BFIN_BUILTIN_CPLX_MAC_16
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|| fcode == BFIN_BUILTIN_CPLX_MSU_16)
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emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, accvec, const0_rtx,
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const0_rtx,
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GEN_INT (MACFLAG_W32)));
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else
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emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx,
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const0_rtx, const0_rtx,
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const1_rtx, accvec, const0_rtx,
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const0_rtx,
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GEN_INT (MACFLAG_NONE)));
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if (fcode == BFIN_BUILTIN_CPLX_MAC_16
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|| fcode == BFIN_BUILTIN_CPLX_MAC_16_S40)
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{
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tmp1 = const1_rtx;
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tmp2 = const0_rtx;
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}
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else
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{
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tmp1 = const0_rtx;
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tmp2 = const1_rtx;
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}
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emit_insn (gen_flag_macv2hi_parts (target, op1, op2, const1_rtx,
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const1_rtx, const1_rtx,
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const0_rtx, accvec, tmp1, tmp2,
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@ -5445,6 +5503,35 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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return target;
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case BFIN_BUILTIN_CPLX_SQU:
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arg0 = CALL_EXPR_ARG (exp, 0);
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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accvec = gen_reg_rtx (V2PDImode);
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icode = CODE_FOR_flag_mulv2hi;
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tmp1 = gen_reg_rtx (V2HImode);
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tmp2 = gen_reg_rtx (V2HImode);
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if (! target
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|| GET_MODE (target) != V2HImode
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|| ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
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target = gen_reg_rtx (V2HImode);
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if (! register_operand (op0, GET_MODE (op0)))
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op0 = copy_to_mode_reg (GET_MODE (op0), op0);
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emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE)));
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emit_insn (gen_flag_mulhi_parts (tmp2, op0, op0, const0_rtx,
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const0_rtx, const1_rtx,
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GEN_INT (MACFLAG_NONE)));
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emit_insn (gen_ssaddhi3_parts (target, tmp2, tmp2, const1_rtx,
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const0_rtx, const0_rtx));
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emit_insn (gen_sssubhi3_parts (target, tmp1, tmp1, const0_rtx,
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const0_rtx, const1_rtx));
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return target;
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default:
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break;
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}
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@ -137,7 +137,8 @@
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(UNSPEC_LSETUP_END 10)
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;; Distinguish a 32-bit version of an insn from a 16-bit version.
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(UNSPEC_32BIT 11)
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(UNSPEC_NOP 12)])
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(UNSPEC_NOP 12)
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(UNSPEC_ONES 12)])
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(define_constants
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[(UNSPEC_VOLATILE_EH_RETURN 0)
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@ -1314,6 +1315,14 @@
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%0 = %1 ^ %2;"
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[(set_attr "type" "alu0")])
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(define_insn "ones"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(unspec:HI [(match_operand:SI 1 "register_operand" "d")]
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UNSPEC_ONES))]
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""
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"%h0 = ONES %1;"
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[(set_attr "type" "alu0")])
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(define_insn "smaxsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(smax:SI (match_operand:SI 1 "register_operand" "d")
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@ -2943,6 +2952,60 @@
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"%h0 = %h1 + %h2 (S)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "ssaddhi3_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(ss_plus:HI (vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
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""
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{
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const char *templates[] = {
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"%h0 = %h1 + %h2 (S)%!",
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"%d0 = %h1 + %h2 (S)%!",
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"%h0 = %d1 + %h2 (S)%!",
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"%d0 = %d1 + %h2 (S)%!",
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"%h0 = %h1 + %d2 (S)%!",
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"%d0 = %h1 + %d2 (S)%!",
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"%h0 = %d1 + %d2 (S)%!",
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"%d0 = %d1 + %d2 (S)%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
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+ (INTVAL (operands[5]) << 2);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "sssubhi3_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(ss_minus:HI (vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
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""
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{
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const char *templates[] = {
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"%h0 = %h1 - %h2 (S)%!",
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"%d0 = %h1 - %h2 (S)%!",
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"%h0 = %d1 - %h2 (S)%!",
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"%d0 = %d1 - %h2 (S)%!",
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"%h0 = %h1 - %d2 (S)%!",
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"%d0 = %h1 - %d2 (S)%!",
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"%h0 = %d1 - %d2 (S)%!",
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"%d0 = %d1 - %d2 (S)%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
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+ (INTVAL (operands[5]) << 2);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "sssubhi3"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(ss_minus:HI (match_operand:HI 1 "register_operand" "d")
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@ -3157,6 +3220,35 @@
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"%h0 = %h1 * %h2 %M3%!"
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[(set_attr "type" "dsp32")])
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(define_insn "flag_mulhi_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
|
||||
(parallel [(match_operand 3 "const01_operand" "P0P1")]))
|
||||
(unspec:HI [(vec_select:HI
|
||||
(match_operand:V2HI 1 "register_operand" "d")
|
||||
(parallel [(match_operand 4 "const01_operand" "P0P1")]))
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 2 "register_operand" "d")
|
||||
(parallel [(match_operand 5 "const01_operand" "P0P1")]))
|
||||
(match_operand 6 "const_int_operand" "n")]
|
||||
UNSPEC_MUL_WITH_FLAG))]
|
||||
""
|
||||
{
|
||||
const char *templates[] = {
|
||||
"%h0 = %h1 * %h2 %M6%!",
|
||||
"%d0 = %h1 * %h2 %M6%!",
|
||||
"%h0 = %d1 * %h2 %M6%!",
|
||||
"%d0 = %d1 * %h2 %M6%!",
|
||||
"%h0 = %h1 * %d2 %M6%!",
|
||||
"%d0 = %h1 * %d2 %M6%!",
|
||||
"%h0 = %d1 * %d2 %M6%!",
|
||||
"%d0 = %d1 * %d2 %M6%!" };
|
||||
int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
|
||||
+ (INTVAL (operands[5]) << 2);
|
||||
return templates[alt];
|
||||
}
|
||||
[(set_attr "type" "dsp32")])
|
||||
|
||||
(define_insn "flag_mulhisi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:HI 1 "register_operand" "d")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user